Method and apparatus for branch target prediction

Details Method and apparatus for branch target prediction Method and apparatus for branch target prediction

1997-11-24

1999-08-17

Eng, David Y.

Electrical computers and digital processing systems: processing

Processing control

Branching

G06F 932

Patent

active

059387610

ABSTRACT:
One embodiment of the present invention provides a method and an apparatus for predicting the target of a branch instruction. This method and apparatus operate by using a translation lookaside buffer (TLB) to store page numbers for predicted branch target addresses. In this embodiment, a branch target address table stores a small index to a location in the translation lookaside buffer, and this index is used retrieve a page number from the location in the translation lookaside buffer. This page number is used as the page number portion of a predicted branch target address. Thus, a small index into a translation lookaside buffer can be stored in a predicted branch target address table instead of a larger page number for the predicted branch target address. This technique effectively reduces the size of a predicted branch target table by eliminating much of the space that is presently wasted storing redundant page numbers. Another embodiment maintains coherence between the branch target address table and the translation lookaside buffer. This makes it possible to detect a miss in the translation lookaside buffer at least one cycle earlier by examining the branch target address table.

REFERENCES:
patent: 4155119 (1979-05-01), DeWard et al.
patent: 5537560 (1996-07-01), Boggs et al.
patent: 5574871 (1996-11-01), Hoyt et al.
patent: 5625788 (1997-04-01), Boggs et al.
patent: 5740415 (1998-04-01), Hara
patent: 5867698 (1999-02-01), Cumming et al.

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