Electrical computers and digital processing systems: processing – Processing control – Branching
Patent
1996-12-30
2000-07-11
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing control
Branching
712233, 712237, 712238, 712239, 712240, G06F 938
Patent
active
060887931
ABSTRACT:
A microprocessor capable of predicting program branches includes a fetching unit, a branch prediction unit, and a decode unit. The fetching unit is configured to retrieve program instructions, including macro branch instructions. The branch prediction unit is configured to receive the program instructions from the fetching unit, analyze the program instructions to identify the macro branch instructions, determine a first branch prediction for each of the macro branch instructions, and direct the fetching unit to retrieve the program instructions in an order corresponding to the first branch predictions. The decode unit is configured to receive the program instructions in the order determined by the branch prediction unit, break down the program instructions into micro-operations, and determine a decoded branch micro-operation corresponding to each of the macro branch instructions requiring verification, such that each of the decoded branch micro-operations has a decoded branch outcome of taken, if the first branch prediction is incorrect, and not taken if the first branch prediction is correct. The microprocessor may also include an execution engine configured to execute the micro-operations and determine the decoded branch outcome for each of the decoded branch micro-operations and communicate each decoded branch outcome of taken to the fetching unit such that the fetching unit can re-retrieve the program instructions in a corrected order corresponding to each incorrect first branch prediction.
REFERENCES:
patent: 4394729 (1983-07-01), Armstrong
patent: 4750112 (1988-06-01), Jones et al.
patent: 4853840 (1989-08-01), Shibuya
patent: 4991080 (1991-02-01), Emma et al.
patent: 5072364 (1991-12-01), Jardine et al.
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5142634 (1992-08-01), Fite et al.
patent: 5155843 (1992-10-01), Stamm et al.
patent: 5163140 (1992-11-01), Stiles et al.
patent: 5179673 (1993-01-01), Steely, Jr. et al.
patent: 5265213 (1993-11-01), Weiser et al.
patent: 5276882 (1994-01-01), Emma et al.
patent: 5283873 (1994-02-01), Steely, Jr. et al.
patent: 5313634 (1994-05-01), Eickemeyer
patent: 5353421 (1994-10-01), Emma et al.
patent: 5355459 (1994-10-01), Matsuo et al.
patent: 5367703 (1994-11-01), Levitan
patent: 5414822 (1995-05-01), Saito et al.
patent: 5434985 (1995-07-01), Emma et al.
patent: 5442756 (1995-08-01), Grochowski et al.
patent: 5542109 (1996-07-01), Blomgren et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5577217 (1996-11-01), Hoyt et al.
patent: 5584001 (1996-12-01), Hoyt et al.
patent: 5589001 (1996-12-01), Maeda et al.
patent: 5592636 (1997-01-01), Popescu et al.
patent: 5608885 (1997-03-01), Gupta et al.
patent: 5664136 (1997-09-01), Witt et al.
patent: 5687338 (1997-11-01), Boggs et al.
patent: 5706492 (1998-01-01), Hoyt et al.
patent: 5796973 (1998-08-01), Witt et al.
patent: 5812839 (1998-09-01), Hoyt et al.
Subroutine Return Address Stack, IBM Technical Disclosure Bulletin, Dec. 1981, vol. 24, No. 7A, pp. 3255-3258.
Highly Accurate Subroutine Stack Prediction Mechanism, IBM Technical Disclosure Bulletin, Mar. 1986, vol. 28, No. 10, pp. 4635-4637.
Subroutine Call/Return Stack, IBM Technical Disclosure Bulletin, Apr. 1988, vol. 30, No. 11, pp. 221-225.
Branch Prediction Strategies and Branch Target Buffer-Design, Johnny K. F. Lee and Alan Jay Smith, Jan. 1984, pp. 6-22.
Superscalar Microprocessor Design, Instruction Fetching and Decoding, Mike Johnson, 1991, pp. 57-85.
Two-Level Adaptive Training Branch Prediction, Tse-Yu Ych and Yale N. Patt, 1991, pp. 51-61.
Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation, Shien-Tai Pan, Kimming So, Joseph T. Rahmeh, 1992, pp. 76-84.
A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution, Tse-Yu Yeh and Yale N. Patt, 1992, pp. 129-139.
Return Address Stack Cache, IBM Technical Disclosure Bulletin, vol. 34, No. 11, Apr. 1992, pp. 269-271.
Alternative Implementations of Two-Level Adaptive Branch Prediction, The 19th Annual International Suymposium on Computer Architecture, The Association for Computing Machinery, pp. 125-134.
Branch History Table Indexing to Prevent Pipeline Bubbles in Wide-Issue superscalar Processors, Tse-Yu Yeh and Yale N. Patt, 1993, pp. 164-175.
A Comparison of Dynamic Branch Predictors That Use Two Levels of Branch History, Tse-Uy Ueh and Yale N. Patt, 1993, pp. 257-266.
Liu Kin-Yip
Mital Millind
Shoemaker Kenneth
An Meng-Ai T.
Intel Corporation
Nguyen Dzung C
Su Gene
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