Method and apparatus for blending bus writes and cache write-bac

Details Method and apparatus for blending bus writes and cache write-bac Method and apparatus for blending bus writes and cache write-bac

1995-12-27

1999-01-12

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711146, G06F 1208

Patent

active

058601120

ABSTRACT:
Apparatus and a method for utilizing a memory bus write buffer to blend up-to-date data stored in a processor cache and being written back to memory with data in the write buffer being written to the same memory address by a bus master in order to maintain data coherency. The circuitry also utilizes the memory bus write buffer to write valid data furnished in a bus master write over up-to-date data in the write buffer being written to the same memory address from a processor cache in order to maintain data coherency. Combining the data from the two sources prior to writing it to memory eliminates at least one write operation by the write controller along with any associated ECC value generation, may eliminate a number of read/modify/write back operations with any associated ECC value generations, and can double the effective depth of the buffer.

REFERENCES:
patent: 5530835 (1996-06-01), Vashi et al.
patent: 5553265 (1996-09-01), Abato et al.
patent: 5572702 (1996-11-01), Sarangdhar et al.

Affiliated with

Also associated with

Rating

Method and apparatus for blending bus writes and cache write-bac does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for blending bus writes and cache write-bac, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for blending bus writes and cache write-bac will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1525194