Method and apparatus for bit line isolation for random access me

Details Method and apparatus for bit line isolation for random access me Method and apparatus for bit line isolation for random access me

1998-10-30

2000-03-07

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365207, 36518909, 36518911, G11C 702

Patent

active

060349093

ABSTRACT:
A circuit for controlling isolation transmission gates connected to the bit lines of a dynamic random access memory (DRAM) device. The circuit includes tri-state circuits which selectively configure transmission gate impedance. The transmission gates are configured for low impedance when stored data is provided to the bit lines. The transmission gates are configured for intermediate impedance when the bit lines are driven towards reference voltage levels. Further, the transmission gates are configured for high impedance to isolate the sense amplifiers from blocks of memory cells that are not involved in the execution of an access to a row of memory cells.

REFERENCES:
patent: 4933907 (1990-06-01), Kumanoya et al.
patent: 4984217 (1991-01-01), Sato
patent: 5777934 (1998-07-01), Lee et al.
patent: 5781497 (1998-07-01), Patel et al.

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