Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-01-15
2001-06-12
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000
Reexamination Certificate
active
06247083
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and to an apparatus for transferring bi-directionally data between an IEEE 1394 bus and a device to be controlled by said bus.
BACKGROUND OF THE INVENTION
The IEEE 1394 bus is a low cost, high performance serial bus. It has a read/write memory architecture and a highly sophisticated communication protocol. Data rates of 100, 200 or 400 Mbit/s can be transmitted in nearly real time. Simultaneously, data can be transmitted bi-directionally. The first ten bits of transmitted address values refer to one of up to 1023 possible IEEE 1394 bus clusters. The following six bits of the transmitted address values refer within a specific cluster to one of up to 63 nodes to which an application or device is assigned. Data between nodes can be exchanged without interaction of a host controller. Devices can be connected to or disrupted from the network at any time, allowing a plug and play behavior.
The standardized cable connection for the nodes has a length of 4.5 m and contains three twisted cable pairs of which two pairs serve for data and control information transmission and the further pair carries supply voltages of 8V to 40V. Three level coding is used: HIGH (H), LOW (L), and HIGH IMPEDANCE (Z). H overrides L, L overrides Z. The characteristic impedance is 110 &OHgr;. There is also a version IEEE 1394-1995 of the bus specification including only two twisted pairs of cables on which no power supply voltage is present. The communication protocol has three layers: physical layer, link layer, and transaction layer. Typically, the transaction layer is realized by firmware whereas the other layers are implemented using chip sets.
The physical layer contains analog transceivers and a digital state machine. It handles bus auto-configuration and hot plug. It reclocks, regenerates and repeats all packets and forwards all packets to the local link layer. It carries out-packet framing, for example speed code, prefix, and packet end assembling. It arbitrates and transmits packets from the local link layer. Available integrated circuit (“IC”) types are e.g. TSB11C01, TSB11LV01, TSB21LV03, and TSB41LV03 of Texas Instruments, MB86611 of Fujitsu, and 21S750 of IBM.
The link layer performs all digital logic. It recognizes packets addressed to the node by address recognition and decodes the packet headers. It delivers packets to higher layers and generates packets from higher layers. It works either isochronous for AV data use or asynchronous for control data use.
In the isochronous mode a channel having a guaranteed bandwidth is established. There is a defined latency. The transmission is performed in 125 &mgr;s time slots or cycles. Headers and data blocks of a packet have separate CRCs (cyclic redundancy check). This mode has a higher priority than the asynchronous data transfer mode.
The asynchronous mode is not time critical, but safe. It operates as an acknowledged service with a busy and retry protocol. Fixed addresses are used. Transmission takes place when the bus is idle. The asynchronous mode handles read request/response, write request/response, and lock request/response. It performs cycle control, CRC generation and validation. Available link layer IC types are e.g. TSB12C01A, TSB12LV21, TSB12LV31, and TSB12LV41 of Texas Instruments, and PDI1394L11 of Philips.
The transaction layer implements asynchronous bus transactions:
Read request/read response
Write request/write response
Lock request/lock response
As mentioned above it can be implemented by software running on a microcontroller, such as e.g. the i960 of SparcLite.
There may also be an AV (audio video) layer carrying out device control, connection management, timestamping, and packetizing.
SUMMARY OF THE INVENTION
The link layer IC usually contains a FIFO (first in first out) memory having a capacity of e.g. 32k or 64k bits and further buffers and adapts the data coming from the application to the requirements of the IEEE 1394 bus specification. Therefore, the link layer chip contains a lot of circuitry and is the most costly part of a complete IEEE 1394 interface. Due to these cost reasons most ICs on the market are not bi-directional although the IEEE 1394 bus specification supports this feature. Incoming or outgoing data packets are intermediately stored in the FIFO.
It is true that some link layer ICs are bi-directional, but for a lot of applications, e.g. video data operation, the memory size of such standard bi-directional link ICs is sufficient only for either transmission or reception of isochronous data at any one time. Therefore, in practice, such ICs can only be used in one direction, i.e. real-time bi-directional data transfer is not possible. A larger memory size was not chosen for such standard link ICs, because no necessity for real-time bi-directional data transfer was seen which would justify the additional costs. The current solution to this problem is to have two separate IEEE 1394 bus nodes assigned to the same application, the two nodes including two physical layer ICs, two link layer ICs, two microcontrollers, and an additional cable connection, i.e. a quite complicated and expensive solution. The physical separation of the two nodes adds to the network latency and requires an additional cable hop. Because only 16 cable hops are allowed in the IEEE 1394 bus specification the latter requirement can cause a significant drawback in some applications.
It is one object of the invention to disclose a method for combining widely available, and therefore cheap, uni-directional IEEE 1394 bus link layer ICs to form a bi-directional data transfer functionality for an IEEE 1394 bus interface representing only one IEEE 1394 bus node.
It is a further object of the invention to disclose an apparatus which utilizes the inventive method.
The inventors have found, confirmed by simulations, that although the physical link layer interface is not designed for this purpose, it works correctly with up to three link layer ICs and one physical layer IC if the additional link layer IC/ICs is/are programmed respectively.
According to the invention, two or more link layer ICs operate together with one physical layer IC in one node wherein the link layer ICs are connected to the same application or device. Advantageously, all link layer ICs, the physical layer IC and the application can be controlled by a single microcontroller performing e.g. software control and bus management. Link ICs can be selectively addressed using e.g. a unique I2C bus address or host chip enable.
The invention allows simultaneous real-time input and output of data packets or simultaneous input of two data packets, e.g. the reception of a video channel and an audio channel or the reception of two video channels, for instance for PIP (picture-in-picture) purposes.
In principle, the inventive method is suited for transferring bi-directionally data between an IEEE 1394 bus and a device to be controlled by said bus, wherein for interfacing between the bus and said device a physical layer IC and a first link layer IC is used and wherein a second link layer IC is also in operation which is connected on one side to the interface input/output of said first link layer IC and on the other side to said device,
wherein said first link layer IC performs input and output of bus-related data and said second link layer IC performs either input or output of bus-related data or
wherein said first link layer IC performs input of first bus-related data and said second link layer IC performs input of second bus-related data and wherein said first and second bus-related data belong to different data streams, in particular two video data streams or one video and one audio data stream.
Advantageous additional embodiments of the inventive method are disclosed in the respective dependent claims.
In principle the inventive apparatus is suited for transferring bi-directionally data between an IEEE 1394 bus and a device to be controlled by said bus, and includes:
a physical layer IC and a first link layer IC for interfacing betwe
Hake Hans-Hermann
Heighway Timothy
Keesen Heinz-Werner
Auve Glenn A.
Duetsche Thomson-Brandt GmbH
Kiel Paul P.
Tripoli Joseph S.
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