Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2002-05-15
2003-04-01
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S005000, C710S006000, C710S036000, C710S039000, C710S040000, C710S240000, C710S244000
Reexamination Certificate
active
06542944
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to multi-path computer systems, and more particularly, to a method and apparatus for balancing workloads among the multiple paths in such a computer system.
DESCRIPTION OF THE RELATED ART
Many computer systems include one or more host computers and one or more system resources with which the host computers communicate. An example of such a system is shown in
FIG. 1
, and includes a host computer
1
and a system resource (i.e., a storage system
3
) with which the host computer
1
communicates to store and retrieve data used by the host computer
1
.
The storage system
3
includes a plurality of storage devices on which data is stored. In the exemplary system shown in
FIG. 1
, the storage system includes a plurality of disk drives
5
a
-
5
b
, and a plurality of disk controllers
7
a
-
7
b
that respectively control access to the disk drives
5
a
and
5
b
. The storage system
3
further includes a plurality of storage bus directors
9
that control communication with the host computer
1
over communication buses
17
. The storage system
3
further includes a cache
11
to provide improved storage system performance. In particular, when the host computer
1
executes a read from the storage system
3
, the storage system
3
may service the read from the cache
11
(when the data is stored in the cache), rather than from one of the disk drives
5
a
-
5
b
, to execute the read more efficiently. Similarly, when the host computer
1
executes a write to the storage system
3
, the corresponding storage bus director
9
can execute the write to the cache
11
. Thereafter, the write can be destaged asynchronously, in a manner transparent to the host computer
1
, to the appropriate one of the disk drives
5
a
-
5
b
. Finally, the storage system
3
includes an internal bus
13
over which the storage bus directors
9
, disk controllers
7
a
-
7
b
and the cache
11
communicate.
The host computer
1
includes a processor
16
and one or more host bus adapters
15
that each controls communication between the processor
16
and the storage system
3
via a corresponding one of the communication buses
17
. It should be appreciated that rather than a single processor
16
, the host computer
1
can include multiple processors. Each bus
17
can be any of a number of different types of communication links, with the host bus adapter
15
and the storage bus directors
9
being adapted to communicate using an appropriate protocol for the communication bus
17
coupled therebetween. For example, each of the communication buses
17
can be implemented as a SCSI bus, with the directors
9
and adapters
15
each including a SCSI driver.
Multiple communication paths typically have been provided for one of two reasons. First, multiple communication paths provide some fault tolerance in the event that one of the communication paths between the host computer
1
and the system resource (e.g., the storage system
3
) experiences a failure. Thus, in some computer systems, only a single communication path is operational at any particular time, but at least one additional path is provided and becomes operational if the primary path experiences a failure.
In other computer systems, multiple communication paths are provided to enhance system performance. In such systems, the multiple communication paths are operated simultaneously, so that multiple communication operations between the host computer
1
and the system resource (e.g., the storage system
3
) can be performed simultaneously to enhance system performance.
In systems wherein multiple communication paths are employed simultaneously, a simple round robin technique has conventionally been employed for balancing the activity over the multiple paths. In particular, a first operation between the host computer
1
and the resource (e.g., the storage system
3
) is performed over a first of the communication paths (e.g., path A in FIG.
1
), the next operation is performed using a next communication path (e.g., path B), and so on until an operation has been performed using each of the communication paths. At that point, the round robin technique wraps around and begins again by transmitting the next operation over the first communication path (e.g., path A). Thus, in the illustrated system of
FIG. 1
, a series of consecutive communication operations between the host computer
1
and the storage system
3
would be performed respectively over the following sequence of paths: A, B, C, D, A, B, C, D, . . . A, B, C, D.
Applicants have discovered that the conventional round robin technique does not maximize system performance. Thus, it is an object of the present invention to provide an improved method and apparatus for balancing activity between multiple paths in a multi-path computer system.
SUMMARY OF THE INVENTION
One illustrative embodiment of the invention is directed to a method for distributing input/output (I/O) operations among at least two paths in a multi-path computer system including a host computer, a system resource and a plurality of paths coupling the host computer to the system resource. The method comprises a step of, for a next I/O operation to be assigned for transmission between the host computer and the system resource, selecting one of the at least two of the plurality of paths for transmission of the next I/O operation based upon a state of previously assigned I/O operations queued for transmission over the at least two of the plurality of paths.
Another illustrative embodiment of the invention is directed to a host computer for use in a multi-path computer system including a system resource and a plurality of paths coupling the host computer to the system resource. The host computer comprises a driver to distribute input/output (I/O) operations initiated by the host computer among at least two of the plurality of paths for transmission to the system resource, the driver selecting, for a next I/O operation to be assigned for transmission from the host computer to the system resource, one of the at least two of the plurality of paths based upon a state of previously assigned I/O operations queued for transmission to the system resource over the at least two of the plurality of paths.
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Annex to Form PCT/ISA/206, Communication Relating to Results of the Partial International Search Report.
“Dynamic I/O Load Balance Task Dispatching Algorithms”, IBM Technical Disclosure Bulletin, vol. 18, No. 8, Jan. 1976.
EMC Corporation
Gaffin Jeffrey
Perveen Rehana
Wolf Greenfield & Sacks P.C.
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