Method and apparatus for balancing load vs. store access to a pr

Details Method and apparatus for balancing load vs. store access to a pr Method and apparatus for balancing load vs. store access to a pr

1998-12-18

2000-12-19

Pan, Daniel H.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

712245, 712248, 712219, 711125, 711132, G06F 1320, G06F 1316, G06F 13362

Patent

active

061638218

ABSTRACT:
A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when there are prior store instructions pending in the store queue. The periodic stalls bias the issue stage to issue load groups and store instruction groups. In the latter case, the store queue is free to update the data cache with the data from previous store instructions. Thus, the invention memory access member biases issuance of store instructions in a manner that prevents the store queue from becoming full, and as such enables the store queue to write to the data cache before the store queue becomes full.

REFERENCES:
patent: 5003463 (1991-03-01), Coyle et al.
patent: 5509130 (1996-04-01), Trauben et al.
patent: 5621896 (1997-04-01), Burgess

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