Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2006-04-25
2008-05-27
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
C712S215000, C712S216000, C712S217000, C712S218000
Reexamination Certificate
active
07380104
ABSTRACT:
A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the particular cycle, one or more instructions in the queue are evaluated to determine if any of them are dependent on the designated instruction. For the evaluation, each instruction placed into the queue is accompanied by corresponding logic elements that provide destination to source compares for the instruction. In an embodiment comprising a method, the oldest ready instruction in the queue during a particular cycle is identified. When an instruction was previously designated to issue during the particular cycle, it is determined whether at least a first instruction in the queue complies with each condition in a set of conditions, the set including at least the conditions that the first instruction has a dependency on the designated instruction, and that the first instruction is older than the oldest ready instruction. The first instruction is selected for issue during the next following cycle only if the first instruction complies with each condition in the set.
REFERENCES:
patent: 5655096 (1997-08-01), Branigin
patent: 5745726 (1998-04-01), Shebanow et al.
patent: 5761476 (1998-06-01), Martell
patent: 5802386 (1998-09-01), Kahle et al.
patent: 6249855 (2001-06-01), Farrell et al.
patent: 6304953 (2001-10-01), Henstrom et al.
patent: 6512397 (2003-01-01), Jacobson et al.
patent: 6697939 (2004-02-01), Kahle
patent: 6728866 (2004-04-01), Kahle et al.
patent: 2001/0042192 (2001-11-01), Le et al.
patent: 2003/0208672 (2003-11-01), Leenstra et al.
patent: 2004/0139299 (2004-07-01), Busaba et al.
patent: 2005/0149698 (2005-07-01), Yeh et al.
patent: 2007/0074005 (2007-03-01), Abernathy et al.
Subbarao Palacharla, Norman P. Jouppi, James E. Smith, “Quantifying the Complexity of Superscalar Processors”, Year= 1996, pp. 1 to 47.
Burky William Elton
Yeung Raymond Cheung
Alrobaye Idriss
Chan Eddie P
International Business Machines - Corporation
Salys Cas K.
Skarsten James O.
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