Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2007-08-28
2007-08-28
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C712S218000
Reexamination Certificate
active
10923219
ABSTRACT:
One embodiment of the present invention provides a system that avoids read-after-write (RAW) hazards while speculatively executing instructions on a processor. The system starts in a normal execution mode, wherein the system issues instructions for execution in program order. Upon encountering a stall condition during execution of an instruction, the system generates a checkpoint, and executes the instruction and subsequent instructions in a speculative-execution mode. The system also maintains dependency information for each register indicating whether or not a value in the register depends on an unresolved data-dependency. The system uses this dependency information to avoid RAW hazards during the speculative-execution mode.
REFERENCES:
patent: 2002/0087794 (2002-07-01), Jouppi et al.
patent: WO 2004/059472 (2004-07-01), None
patent: WO 2005/106648 (2005-11-01), None
“Beating in-order stalls with “flea-flicker” two-pass pipelining”, by Ronald D. Barnes et al., Proceedings of the 36thInternational Symposium on Microarchitecture, 2003 IEEE.
Caprioli Paul
Chaudhry Shailender
Tremblay Marc
Ellis Richard L.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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