Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2006-06-27
2006-06-27
Vo, Tim (Department: 2112)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000
Reexamination Certificate
active
07069367
ABSTRACT:
An embodiment of a system for avoiding race conditions when using edge-triggered interrupts includes a processor that asserts an interrupt pending signal in response to the receipt of an edge-triggered interrupt. A power management device receives the interrupt pending signal. If the processor is in a low power state when it asserts the interrupt pending signal, then the power management device causes the processor to enter a high power state to allow the processor to service the pending interrupt.
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Cline Leslie E.
Poisner David I.
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