Method and apparatus for avoiding back-to-back data rewrites to

Details Method and apparatus for avoiding back-to-back data rewrites to Method and apparatus for avoiding back-to-back data rewrites to

1996-08-08

1998-04-07

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Resistive

365100, 365195, G11C 1300

Patent

active

057372624

ABSTRACT:
In a memory system, a first write address is initially loaded into a first latch and transferred to a second latch. A second write address is then loaded into the first address latch. The two addresses are then compared and, if they differ, data associated with the first address is stored in a memory array. However, if the addresses are the same, it is assumed that the user intended to discard the first data associated with that address and this data is discarded rather than being stored in the array. After the comparison, the second address overwrites the first address in the second latch. A third write address is then loaded in the first latch. A comparison is made again, and data associated with the second address is stored in the array only if the second and third addresses are different, otherwise the original data associated with the second address is discarded. This process is repeated for each write address sent to the memory system.

REFERENCES:
patent: 4014007 (1977-03-01), Groeger
patent: 4442507 (1984-04-01), Roesner
patent: 4685088 (1987-08-01), Iannucci
patent: 4795657 (1989-01-01), Formigoni et al.
patent: 5097445 (1992-03-01), Yamauchi
patent: 5406509 (1995-04-01), Ovshinsky et al.
patent: 5493665 (1996-02-01), Eisenberg
patent: 5541869 (1996-07-01), Rose et al.

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