Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-09-26
2006-09-26
Sparks, Donald (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S130000, C711S144000, C711S145000, C712S244000
Reexamination Certificate
active
07114036
ABSTRACT:
A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, when it is determined that a cache line is being falsely shared using the performance indicators and counters, an interrupt may be generated and sent to a performance monitoring application. An interrupt handler of the performance monitoring application will recognize this interrupt as indicating false sharing of a cache line. Rather than reloading the cache line in a normal fashion, the data or instructions being accessed may be written to a separate area of cache or memory area dedicated to false cache line sharing data. The code may then be modified by inserting a pointer to this new area of cache or memory. Thus, when the code again attempts to access this area of the cache, the access is redirected to the new cache or memory area rather than to the previous area of the cache that was subject to false sharing. In this way, reloads of the cache line may be avoided.
REFERENCES:
patent: 4291371 (1981-09-01), Holtey
patent: 5103394 (1992-04-01), Blasciak
patent: 5691920 (1997-11-01), Levine et al.
patent: 5710881 (1998-01-01), Gupta et al.
patent: 5774724 (1998-06-01), Heisch
patent: 5822763 (1998-10-01), Baylor et al.
patent: 5928334 (1999-07-01), Mandyam et al.
patent: 5930508 (1999-07-01), Faraboschi et al.
patent: 5937437 (1999-08-01), Roth et al.
patent: 5938778 (1999-08-01), John, Jr. et al.
patent: 5966537 (1999-10-01), Ravichandran
patent: 5987250 (1999-11-01), Subrahmanyam
patent: 6070009 (2000-05-01), Dean et al.
patent: 6094709 (2000-07-01), Baylor et al.
patent: 6101524 (2000-08-01), Choi et al.
patent: 6134676 (2000-10-01), VanHuben et al.
patent: 6149318 (2000-11-01), Chase et al.
patent: 6185671 (2001-02-01), Pentovski et al.
patent: 6189141 (2001-02-01), Benitez et al.
patent: 6192513 (2001-02-01), Subrahmanyam
patent: 6206584 (2001-03-01), Hastings
patent: 6223338 (2001-04-01), Smolders
patent: 6243804 (2001-06-01), Cheng
patent: 6247113 (2001-06-01), Jaggar
patent: 6256775 (2001-07-01), Flynn
patent: 6285974 (2001-09-01), Mandyam et al.
patent: 6286132 (2001-09-01), Tanaka et al.
patent: 6324689 (2001-11-01), Lowney et al.
patent: 6330662 (2001-12-01), Patel et al.
patent: 6351844 (2002-02-01), Bala
patent: 6374364 (2002-04-01), McElroy et al.
patent: 6430741 (2002-08-01), Mattson, Jr. et al.
patent: 6442585 (2002-08-01), Dean et al.
patent: 6446029 (2002-09-01), Davidson et al.
patent: 6460135 (2002-10-01), Suganuma
patent: 6480938 (2002-11-01), Vondran, Jr.
patent: 6636950 (2003-10-01), Mithal et al.
patent: 6842850 (2005-01-01), Ganapathy et al.
patent: 6944720 (2005-09-01), Sperber et al.
patent: 7035996 (2006-04-01), Woodall et al.
patent: 2001/0032305 (2001-10-01), Barry
patent: 2002/0019976 (2002-02-01), Patel et al.
patent: 2002/0124237 (2002-09-01), Sprunt et al.
patent: 2002/0129309 (2002-09-01), Floyd et al.
patent: 2002/0147965 (2002-10-01), Swaine et al.
patent: 2002/0199179 (2002-12-01), Lavery et al.
patent: 2003/0126590 (2003-07-01), Burrows et al.
patent: 2004/0205302 (2004-10-01), Cantrill
patent: 2000029731 (1999-12-01), None
patent: 2000347863 (2000-12-01), None
Torrellas et al., “False Sharing and Spatial Locality in Multiprocessor Caches”, Jun. 1994, IEEE Transactions on Computers, vol. 43, No. 6, pp. 651-663.
Rothman et al., “Analysis of Shared Memory Misses and Reference Patterns”, 2000, IEEE, pp. 187-198.
Cohen et al., “Hardware-Assisted Characterization of NAS Benchmarks”, Cluster Computing, vol. 4, No. 3, Jul. 2001, pp. 189-196.
Talla et al., “Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Super Scaler Architectures”, International Conference on Computer Design, Austin, Sep. 17-20, 2000, pp. 163-172.
Iwasawa et al., “Parallelization Method of Fortran DO Loops by Parallelizing Assist System”, Transactions of Information Processings Society of Japan, vol. 36, No. 8, Aug. 1995, pp. 1995-2006.
Talla et al., “Execution Characteristics of Multimedia Applications on a Pentium II Processor”, IEEE International Performance, Computing, and Communications Conference, 19th, Phoenix, Feb. 20-22, 2000, pp. 516-524.
IBM Research Disclosure Bulletin 444188, “Enable Debuggers as an Objective Performanc Measurement Tool for Software Development Cost Reduction”, Apr. 2001, pp. 686-688.
U.S. Appl. No. 09/435,069, Davidson et al., Method and Apparatus for Instruction Sampling for Performance Monitoring and Debug, filed Nov. 4, 1999.
U.S. Appl. No. 08/538,071, Gover et al., Method and System for Selecting and Distinguishing an Event Sequence using an Effective Address in a Pr cessing System, filed Oct. 2, 1995.
U.S. Appl. No. 10/675,777, DeWitt, Jr. et al., Method and Apparatus for Counting Instruction Execution and Data Accesses, filed Sep. 30, 2003.
U.S. Appl. No. 10/674,604, DeWitt, Jr. et al., Method and Apparatus for Selectively Counting Instructions and Data Accesses, filed Sep. 30, 2003.
U.S. Appl. No. 10/675,831, DeWitt, Jr. et al., Method and Apparatus for Generating Interrupts Upon Execution of Marked Instructions and Upon Access to Marked Memory Locations, filed Sep. 30, 2003.
U.S. Appl. No. 10/675,778, DeWitt, Jr. et al., Method and Apparatus for Counting Data Accesses and Instruction Executions that Exceed a Threshold, filed Sep. 30, 2003.
U.S. Appl. No. 10/675,776, DeWitt, Jr. et al., Method and Apparatus for Counting Execution of Specific Instructions and Accesses to Specific Data Locations, filed Sep. 30, 2003.
U.S. Appl. No. 10/675,751, DeWitt, Jr. et al., Method and Apparatus for Debug Support for Individual Instructions and Memory Locations, filed Sep. 30, 2003.
U.S. Appl. No. 10/675,721, Levine et al., Method and Apparatus to Autonomically Select Instructions for Selective Counting, filed Sep. 30, 2003.
U.S. Appl. No. 10/674,642, Levine et al., Method and Apparatus to Autonomically Count Instruction Execution for Applications, filed Sep. 30, 2003.
U.S. Appl. No. 10/674,606, Levine et al., Method and Apparatus to Autonomically Take an Execution on Specified Instructions, filed Sep. 30, 2003.
U.S. Appl. No. 10/675,783, Levine et al., Method and Apparatus to Autonomically Profile Applications, filed Sep. 30, 2003.
U.S. Appl. No. 10/675,872, DeWitt, Jr. et al., Method and Apparatus for Counting Instruction and Memory Location Ranges, filed Sep. 30, 2003.
U.S. Appl. No. 10/757,250, Levine et al., Method and Apparatus for Maintaining Performance Monitoring Structures in a Page Table for use in Monitoring Performance of a Computer Program, filed Jan. 14, 2004.
U.S. Appl. No. 10/757,192, DeWitt, Jr. et al., Method and Apparatus for Providing Pre and Post Handlers for Recording Events, filed Jan. 14, 2004.
U.S. Appl. No. 10/757,249, DeWitt, Jr. et al., Method and Apparatus for Identifying False Cache Line Sharing, filed Jan. 14, 2004.
U.S. Appl. No. 10/757,197, DeWitt, Jr. et al., Method and Apparatus for Optimizing Code Execution Using Annotated for Trace Information having Performance Indicator and Counter Information, filed Jan. 14, 2004.
DeWitt, Jr. Jimmie Earl
Levine Frank Eliot
Richardson Christopher Michael
Urquhart Robert John
International Business Machines - Corporation
Lammes Francis
Rodriguez Herman
Savla Arpan
Sparks Donald
LandOfFree
Method and apparatus for autonomically moving cache entries... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for autonomically moving cache entries..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for autonomically moving cache entries... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3560349