Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-10-21
2000-08-08
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714764, 710 39, 710 40, G06F 1108
Patent
active
061016144
ABSTRACT:
The present invention provides a method and apparatus for automatically scrubbing ECC errors in memory upon the detection of a correctable error in data read from memory. This is performed by providing in a memory controller memory control logic for controlling accesses to memory, an ECC error checking and correcting unit for checking data read from memory for errors and correcting any correctable errors found in the read data, a first data buffer for storing the corrected read data output from the ECC error checking and correcting unit and a writeback path having an input end coupled to an output of the first data buffer and an output end coupled to memory. Upon the detection of a correctable error in data read from a particular memory location, the ECC error checking and correcting unit signals to the memory control logic the existence of a correctable error in the read data. The memory control logic then obtains exclusive control over the first data buffer and the writeback path to control writing of the corrected read data onto the writeback path and subsequently to memory.
REFERENCES:
patent: 4506362 (1985-03-01), Morley
patent: 4535455 (1985-08-01), Peterson
patent: 4604750 (1986-08-01), Manton et al.
patent: 4888773 (1989-12-01), Arlington et al.
patent: 4899342 (1990-02-01), Potter et al.
patent: 4920539 (1990-04-01), Albonesi
patent: 4964129 (1990-10-01), Bowden, III et al.
patent: 4964130 (1990-10-01), Bowden, III et al.
patent: 5127014 (1992-06-01), Raynham
patent: 5233616 (1993-08-01), Callander
patent: 5263032 (1993-11-01), Porter et al.
patent: 5267242 (1993-11-01), Lavallee et al.
patent: 5274645 (1993-12-01), Idelman et al.
patent: 5274646 (1993-12-01), Brey et al.
patent: 5325375 (1994-06-01), Westberg
patent: 5367526 (1994-11-01), Kong
patent: 5367689 (1994-11-01), Mayer et al.
patent: 5388108 (1995-02-01), Demoss et al.
patent: 5392302 (1995-02-01), Kemp et al.
patent: 5410545 (1995-04-01), Porter et al.
patent: 5428630 (1995-06-01), Weng et al.
patent: 5430742 (1995-07-01), Jeddeloh et al.
patent: 5459839 (1995-10-01), Swarts et al.
patent: 5490155 (1996-02-01), Abdoo et al.
patent: 5588112 (1996-12-01), Dearth et al.
patent: 5644583 (1997-07-01), Garcia et al.
Slater, M., "Microprocessor-Based Design", Mayfield Publishing Company, 1987, p. 239.
van de Goor, A.J., "Computer Architecture and Design", Addison-Wesley Publishing Company, 1989, pp. 255-263.
Abstract of Japan, "Memory Control Unit", Nishimura Hiroyuki, Application date: Oct. 16, 1978, Application No. 55055499, Publication date: Apr. 23, 1980.
Supplementary European Search Report, EP95921376, date of search Aug. 25, 1997.
Gonzales Mark A.
Holman Thomas J.
Stolt Patrick F.
Baderman Scott T.
Beausoliel, Jr. Robert W.
Intel Corporation
LandOfFree
Method and apparatus for automatically scrubbing ECC errors in m does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for automatically scrubbing ECC errors in m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for automatically scrubbing ECC errors in m will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1160795