Method and apparatus for automatically generating hardware...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C717S152000, C717S150000, C717S159000, C717S140000, C717S141000

Reexamination Certificate

active

07000213

ABSTRACT:
Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.

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Malay Haldar, Anshuman Nayak, Alok Choudhary and Prith Banerjee: Automated Synthesis Of Pipelined Designs On FPGAS For Signal And Image Processing Applications Described In MATLAB; Proc. of Asia Pacific Design Automation Conference (ASP-DAC) Jan., 2001; 4 pages ; MACH Design Systems, Inc. Schaumberg, IL USA.
Malay Haldar, Anshuman Nayak, Alok Choudhary and Prith Banerjee: FPGA Hardware Synthesis From MATLAB; VLSI Design Conference, Bangalore, India; Jan. 2001, 8 pages, Center For Parallel and Distributed Computing, Northwestern University, Evanston, IL 60208-3118 USA.

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