Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-14
2006-02-14
Thompson, A. M. (Department: 2815)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C717S152000, C717S150000, C717S159000, C717S140000, C717S141000
Reexamination Certificate
active
07000213
ABSTRACT:
Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.
REFERENCES:
patent: 5440244 (1995-08-01), Richter et al.
patent: 5535342 (1996-07-01), Taylor
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6233540 (2001-05-01), Schaumont et al.
patent: 2002/0100029 (2002-07-01), Bowen
patent: 10078973 (1998-03-01), None
P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C Bachmann, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, D. Zargtsky; A MATLAB Compiler For Distributed, Heterogeneous, Reconfigurable Computing Systems, Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 00, Apr. 2000, 10 pages, Electrical and Computer Engineering ; Northwestern University, Evanston, IL-60208-USA.
Malay Haldar, Anshuman Nayak, Alok Choudhary and Prith Banerjee: Automated Synthesis Of Pipelined Designs On FPGAS For Signal And Image Processing Applications Described In MATLAB; Proc. of Asia Pacific Design Automation Conference (ASP-DAC) Jan., 2001; 4 pages ; MACH Design Systems, Inc. Schaumberg, IL USA.
Malay Haldar, Anshuman Nayak, Alok Choudhary and Prith Banerjee: FPGA Hardware Synthesis From MATLAB; VLSI Design Conference, Bangalore, India; Jan. 2001, 8 pages, Center For Parallel and Distributed Computing, Northwestern University, Evanston, IL 60208-3118 USA.
Banerjee Prithviraj
Choudhary Alok
Haldar Malay
Nayak Anshuman
Chu Chris C.
Northwestern University
The Law Office of Deepti Panchawagh-Jain
Thompson A. M.
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