Method and apparatus for automatically eliminating inferred...

Details Method and apparatus for automatically eliminating inferred... Method and apparatus for automatically eliminating inferred...

2005-06-07

2005-06-07

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06904574

ABSTRACT:
Method and apparatus for automatically eliminating inferred latches created by hardware design language (HDL) source code is described. A node tree is built from the HDL source code based on the HDL's Language Reference Manual. The node tree is scanned to identify one or more conditional logic constructs that are sources for creation of inferred latches. A modified node tree is generated by automatically adding and/or modifying sub-productions of the conditional language constructs that create the inferred latches.

REFERENCES:
patent: 6295636 (2001-09-01), Dupenloup
patent: 6571375 (2003-05-01), Narain et al.
patent: 6609229 (2003-08-01), Ly et al.
patent: 2003/0023941 (2003-01-01), Wang et al.
patent: 2003/0037305 (2003-02-01), Chen et al.

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