Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-02-23
2001-09-11
Phan, Trong (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06289489
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of hardware description languages (HDLs). More particularly, this invention relates to the art of cross-referencing HDL statements and corresponding graphical objects.
BACKGROUND
Hardware description languages (HDLs), such as Verilog and very high speed integrated circuit (VHSIC) hardware description language (VHDL), are widely used to develop integrated circuits. HDLs can provide functional and/or structural descriptions of virtually any circuit design in a textual format similar to a high level programming language such as C++ or Pascal. From a HDL representation, a circuit design can be simulated or synthesized using a wide variety of commonly available software and hardware products.
Although HDLs are very powerful tools, the learning curve can be long. Memorizing syntax, managing files, and debugging designs can be incredibly time consuming and frustrating for even experienced users. Users may also have trouble communicating design intent, and modifying existing designs, based on purely textual representations.
Graphical entry of HDL designs can improve the learning curve as well as make design intent easier to communicate to others. In a graphical entry environment, flowcharts, block diagrams, state diagrams, etc. can be created to describe a circuit at a higher level of abstraction. From graphical objects, HDL statements can be generated automatically and used for simulation and/or synthesis.
Graphical entry, however, adds a layer of complexity to the design flow. Although many users prefer to work in a graphical environment, the added layer of complexity can detract from the advantages afforded by graphical entry under certain circumstances, such as debugging or modifying a design.
For example, simulation is usually based on a HDL textual representation. In which case, error messages generated during simulation may refer to particular HDL statements using file pathnames and line numbers. Since the HDL text statements are automatically generated from graphical objects, an inexperienced user may not be able to edit a design directly from the HDL textual representation. And, even if a user is able to edit the HDL text, the graphical representation would no longer accurately represent the design being simulated. For either reason, a user may choose to correct the error using the graphical representation. In which case, the user may first have to manually determine which of potentially thousands of graphical objects corresponds to a particular error message before correcting the error.
Whenever a user has to spend time cross-referencing generated HDL statements to a graphical object or vice versa, advantages gained by designing in a graphical environment may be diminished. Therefore, the usability and productivity of graphical entry may be increased by providing an improved method and apparatus to cross-reference graphical objects and HDL statements.
SUMMARY OF THE INVENTION
The present invention beneficially provides a method and apparatus for cross-referencing graphical objects and hardware description language (HDL) statements. According to one aspect of the present invention, a cross-referencing record is automatically generated to map graphical objects to corresponding HDL statements. According to a second aspect of the invention, a request is received to cross-reference a HDL statement and a graphical object. Based on the request, the cross-referencing record is accessed to identify a target of the request.
REFERENCES:
patent: 5623418 (1997-04-01), Rostoker et al.
Bold Stephen L.
Dane Mark W. P.
Paraskeva Mark
Reynolds Michael J.
Stewart James
Columbia IP Law Group, PC
Phan Trong
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