Method and apparatus for automatically checking circuit...

Details Method and apparatus for automatically checking circuit... Method and apparatus for automatically checking circuit...

2007-10-09

2007-10-09

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10875997

ABSTRACT:
A method and apparatus for checking topology layout routing is described. A method for checking topology layout routing includes accessing actual topology layout information of a circuit. Then, compliance topology information is established. Then, the method checks the actual topology layout information complies with the compliance topology information. Then, the method presents violations of the compliance topology information.

REFERENCES:
patent: 5787006 (1998-07-01), Chevallier et al.
patent: 6898770 (2005-05-01), Boluki et al.
patent: 2002/0188920 (2002-12-01), Lampaert et al.
patent: 2004/0078773 (2004-04-01), Sharma et al.

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