Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-02
2004-07-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06760897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and an apparatus for automatic wiring design between block circuits of an integrated circuit and a program for performing the same method.
2. Description of the Related Art
As the latest semiconductor integration circuit becomes to have higher integration density and larger scale, the number of wires increases and also a demand arises for much narrower wire region and much higher integration density thereof.
FIG. 12
is a view for illustrating a conventional method for automatic wiring design between block circuits of an integrated circuit.
As shown in this figure, inter-block wires
12
and
13
are disposed between circuit blocks
10
and
11
, terminals
101
and
102
are formed along a side
10
S of the circuit block
10
which faces the circuit block
11
, and terminals
111
and
112
are formed along a side
11
S of the circuit block
11
which faces the circuit block
10
. A contact hole
101
C is formed at a cross portion between the inter-block wire
12
and a wire
101
L extended from the terminal
101
, and is connected to the wire
101
L. Similarly, a contact hole
112
C is formed at a cross portion between the inter-block wire
12
and a wire
112
L extended from the terminal
112
, and is connected to the wire
112
L. Through these contact holes
101
C and
102
C, the block wire
12
is connected to the wires
101
L and
112
L belonging to upper or lower wire layers, respectively. The terminal
101
, the wire
101
L, the contact hole
101
C, the inter-block wire
12
, the contact hole
112
C, the wire
112
L and the terminal
112
belong to a same net.
In a case where the terminal
102
, the inter-block wire
13
and the terminal
111
belong to a same net, the terminal
111
and the inter-block wire
13
can be connected to each other as shown in this figure, but the terminal
102
and the inter-block wire
13
cannot be connected to each other. Wiring layout processes has already been performed for the inside of the circuit blocks
10
and
11
, and the block information in the inter-block wiring is given only about the frame and the terminal of the block, and therefore wire extension from the terminal to the internal of the block is forbidden in the inter-block wiring.
Thus, the prior art employs a method as shown in
FIG. 13
where interval between the circuit blocks
10
and
11
is made widened; a wire
102
L is extended and bent from the terminal
102
; a contact hole
102
C is formed at a cross portion between the wire
102
L and the inter-block wire
13
; and the wire
102
L and the inter-block wire
13
are connected to each other through the contact hole
102
C. This falls into increasing the wiring area between the circuit blocks
10
and
11
and also changing the wiring area between the circuit block
10
or
11
and other circuit blocks not shown, causing the rewiring. In order to avoid this problem, a manual connection must be carried out between the blocks in the layout state shown in
FIG. 12
, but it requires much longer time in design.
In addition, in a case where the terminals
102
and
112
and the inter-block wire
12
belong to a same net as shown in
FIG. 14
, if the terminal
112
and the inter-block wire
12
are first connected to each other through the wire
112
L, a contact hole
112
C is formed in the same size as the width of the terminal
112
. Therefore, when the terminal
102
and the contact hole
112
C are connected to each other through the wire
102
L, the wire resistance is increased due to the insufficient area of the contact hole
112
C, which causes increase in the signal delay and timing error. In a case where the wire is used for supplying the power supply, the increased wire resistance lowers the supplied voltage and the electromigration tolerance, resulting in reducing the reliance of the integration circuit.
In order to avoid these problems, a method can be considered as shown in
FIG. 15
where the area between the circuit blocks
10
and
11
is secured in advance two times as that in the case shown in
FIG. 12
; additional inter-block wires
12
A and
13
A are disposed parallel to the inter-block wires
12
and
13
; the inter-block wires
12
A and
13
A are connected to the inter-block wires
12
and
13
, respectively; the inter-block wires
12
and
13
are used for connection with the terminals of the circuit block
10
; and the inter-block wires
12
A and
13
A are used for connection with the terminals of the circuit block
11
. However, this method leads to increase in the inter-block area.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method and an apparatus for automatic wiring design between block circuits of an integrated circuit and a program for performing the same method, which gives priority order to wring so as to reduce manual processes by decreasing the number of not-connected wires as a result of the automatic wiring process, and also reduce the wiring area required to form the inter-block wiring.
In one aspect of the present invention, there is provided a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other, the method comprising the steps of:
(a) sorting the terminals according to the width thereof; and
(b) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.
According to this method, the connection is made for the block terminals in descending order of the width thereof, and therefore the length of extended wire from larger width terminals becomes shorter, which allows reducing the inter-block wiring area. In addition, because forming the contact hole is also performed in descending order of the width thereof, it can be avoided that a larger width wire is connected to a smaller width contact hole.
In another aspect of the present invention, the method for automatic wiring design between block circuits of an integrated circuit comprises the steps of:
(a) sorting the terminals, connected to a power supply wire, according to the value of electric current passing through the terminals; and
(b) selecting a terminal from the terminals in descending order of the value of electric current and connecting between the selected terminal and an inter-block wire belonging to a same net as the selected terminal.
According to this method, the connection is made for the terminal having larger current value, earlier than the terminal having smaller current value even though they have the same width. This allows the length of a wire, which connects between the terminal having larger current value and the inter-block wire, to be shorter than a wire which connects between the terminal having smaller current value and the inter-block wire. Therefore the whole electromigration tolerance of an integrated circuit is improved compared with a case where the connection is made in inverse order. Further, this can prevent the voltage reduction due to the wire resistance.
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patent: 6281529 (2001-08-01), Watanabe
patent: 6492736 (2002-12-01), Chan et al.
patent: 6496968 (2002-12-01), Yamada et al.
patent: 6504187 (2003-01-01), Furuichi
patent: 2002/0038448 (2002-03-01), Ichimiya et al.
patent: 2002/0095643 (2002-07-01), Shiratori
patent: 2002/0127782 (2002-09-01), Fukui et al.
patent: 2002/0149116 (2002-10-01), Kusumoto
Arakawa Toshio
Honda Hiroyuki
Kobayashi Kenji
Miura Daisuke
Nagasaka Mitsuaki
Dimyan Magid Y.
Fujitsu Limited
Siek Vuthe
Staas & Halsey , LLP
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