Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-10-22
2003-12-02
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S014000
Reexamination Certificate
active
06658597
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to recovery of integrated circuits comprising microprocessors (or microcontrollers) which have received an electrical transient voltage resulting from an electrostatic discharge occurring during normal operations or during electromagnetic compatibility testing.
2. Description of the Related Art
Electrostatic discharge (ESD) includes: (1) a localized transfer at the discharge point; (2) inductive coupling between a higher voltage or “charged” object and the discharge object; and (3) electromagnetic radiation from the charged object.
To initiate the correct operations of a microprocessor, a power-on reset circuit is often incorporated within the device to send reset signals to reset the microprocessor to a known state and thus permit execution of the normally desired functions. The failure to power-up in a known state can cause an integrated circuit to function unpredictably. Such unpredictability is particularly undesirable for microprocessors used in, for example, computer keyboards. The following list of U.S. patents and publications provide background information regarding prior art power-on reset circuits; these documents are incorporated by reference herein:
[
1
] S. R. Norsworthy, “CMOS Power-Up Reset Circuit for Gate Arrays and Standard Cells,” U.S. Pat. 4,633,107, December, 1986.
[
2
] C. C. Hanke, C. D. Obregon, and T. W. Sutton, “CMOS Power-On Reset Circuit,” U.S. Pat. No. 4,970,408, November, 1990.
[
3
] R. C. Steele, “Power-Up Reset Circuit,” U.S. Pat. No. 4,983,857, January, 1991.
[
4
] K. L. Wong and J. D. Schutz, “Power-Up Reset Circuit,” U.S. Pat. No. 5,111,067, May, 1992.
[
5
] A. Yukawa, “Power-On-Reset Circuit,” U.S. Pat. No. 5,136,181, August, 1992.
[
6
] S. Tanimoto, “Power On Reset Circuit with Accurate Detection at Low Voltages,”U.S. Pat. No. 5,485,111, January 1996.
[
7
] G. L. Geannopoulos, “Power Up Reset Circuit with Threshold Voltage Shift Protection,” U.S. Pat. No. 5,654,656, August, 1997.
[
8
] C. McClintock and N.Ngo, “Power-On Reset Circuit with Well-Defined Reassertion Voltage,” U.S. Pat. No. 5,821,787, October, 1998.
Known prior art power-on circuits can generate a reset signal to initiate the reset of the microprocessors. The main design principle of such power-on-reset circuits is that a time delay concept is used to generate a reset signal pulse when the integrated circuit is in a power-up or transition phase. Some designs have a low-voltage-detection function, whereby the power-on reset circuits can detect a VDD voltage level drop and subsequently generate another reset pulse to reset the microprocessors. However, such prior art power-on-reset circuit designs are able to detect only low-speed VDD derivations in a time period on the order of milliseconds (ms).
Accordingly, so long as the voltage level of the VDD changes over a time period on the order of ms, the prior art power-on-reset circuits can perform adequate detection of the voltage transition required to reset a microprocessor. However, such prior art power-on-reset circuits cannot detect voltage transitions that occur over a shorter period of time on the order of nanoseconds (ns).
Significantly, the electromagnetic compatibility (EMC) verification of electronic products, such as the system-level ESD (electrostatic discharge) test (so-called “ESD zapping”), the monitor arcing test, and the EFT (electrical fast transition) test, often generate electrical pulses with a time scale on the order of nanoseconds (ns). The standard to verify the system-level ESD test is the “IEC 801-2, Electromagnetic Compatibility for Industrial Process Measurement and Control Equipment, Part 2, Electrostatic Discharge Requirements,” 2
nd
Edition, 1991. The standard to verify the EFT test is the “IEC 1000-4-4, “Electromagnetic Compatibility (EMC), Part 4, Testing and Measurement Techniques Section 4, Electrical Fast Transient/Burst Immunity Test” 1
st
Edition, 1995. Such fast electrical pulses (also referred to as fast electrical transient voltages) can couple into the internal circuits of a microprocessor through an inductance or capacitance coupling and interfere with the operating instructions temporarily stored in the registers, flip-flops, or RAM of the microprocessor.
When the logic states stored in the registers are changed by a coupled fast electrical pulse, the information stored in the registers may become unintelligible. Furthermore, parity values may no longer match because of corruption of the data. If the corrupted logic states are part of a critical function of the microprocessor, it is likely that the microprocessor will, as commonly referred to in the industry, “lock up,” “freeze,” “hang,” or go into a “continuous loop,” while unsuccessfully attempting recovery. It is even possible that a corrupted logic state in the microprocessor caused by a fast electrical pulse may not be discovered until some time afterward when conditions dictate use of those circuits having corrupted logic states. Sometimes, only a complete power-on-reset (which is disruptive to the user) will totally reset all of the latches.
Many products are now being tested for their susceptibility to damage from electrostatic discharge. These electromagnetic compatibility tests may also cause unsuspected problems on the units selected for test. In fact, EMC testing can lead to equipment destruction, yet every circuit during and after the EMC test may remain within the specifications with no apparent permanent parameter changes. However, it is more common that the microprocessor can become upset and/or the electrical system can be frozen after the EMC tests. Most such microprocessors can be restored if the power supply is reset again. However, the executing functions or operating steps of the microprocessor are also reset. In most automated controls for important applications, resetting of the power supply is not an acceptable solution to overcome a detected transient voltage. Therefore, after experiencing electrical interference due to the electromagnetic compatibility verification tests, the microprocessors must recover by themselves without restarting the power supply to achieve an acceptable rating.
Even if an 8-bit microprocessor can sustain a component-level ESD stress of greater than 5 kV , keyboard upset and operational errors have been found in the system-level ESD stress with a 2 kV ESD voltage in the contact-discharge testing method. To meet this system-level ESD specification, some discrete components (such as a magnetic. core, ferrite beads, and RC low-pass circuits) are added into the keyboard circuit board to absorb or bypass the electrical transient due to the system-level ESD test, as shown in the prior art design of FIG.
1
.
FIG. 1
shows a prior art system that absorbs or bypasses the transient voltages by including a series of discrete hardware circuits connected to microprocessor
1
. Ferrite beads
2
are connected to VDD
3
and to VSS
4
. An RC network may also be employed. A series of capacitors
5
coupled to the lines containing the ferrite beads
2
or the resistors
2
a
provide a high frequency short to VSS so that high frequency transient voltages are bypassed. Low frequency voltages representing digitized information pass freely. The keyboard cable
6
comprises a group of current carrying wires that are wrapped around a magnetic core
7
and then connected to the ferrite beads
2
and resistor
2
a
. A high frequency voltage transient will be dropped across (i.e. absorbed by) magnetic core
7
to protect the microprocessor
1
from a transient voltage traveling down the keyboard cable. Some of the drawbacks to this prior art system include the requirement for expensive and bulky discrete components such as the magnetic core and ferrite beads.
Another prior art power-on-reset circuit is disclosed in reference [3]. This circuit is designed so that a logic 1 output will cause an asynchronous reset of all of the registers on
Ker Ming-Dou
Sung Yu-Yu
Beausoliel Robert
Bonzo Bryce P.
Industrial Technology Research Institute
Stevens, Davis, Miller & Mosher, LLP.
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