Method and apparatus for automatic layout of circuit structures

Details Method and apparatus for automatic layout of circuit structures Method and apparatus for automatic layout of circuit structures

2002-04-07

2004-09-07

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06789246

ABSTRACT:

FIELD OF INVENTION
The field of invention relates generally to circuit design and semiconductor manufacturing; and, more specifically, to a method and apparatus for automatically laying out a circuit structure.
BACKGROUND
Transistor Technology
FIGS. 1
a
through
1
c
relate to transistor technology. Transistors are fundamental units of current and/or voltage control in a semiconductor device. As electronic devices (e.g., semiconductor chips) process information by controlling applicable currents and/or voltages (e.g., in digital applications, cutting off current flow so as to represent a binary “0” while allowing current to flow so as to represent a binary “1”), transistors are the fundamental electronic units by which currents and/or voltages are controlled so as to effectively process information.
A semiconductor chip is typically formed by integrating up to millions (and perhaps someday billions) of transistors onto a single “chip” of semiconductor material (e.g., silicon (Si)). By so doing, vast quantities of information can be electronically processed at high speed within relatively small (e.g., thumbnail sized) devices.
FIG. 1
a
shows a standard depiction of what a transistor
101
a
may “look-like” in schematic form (e.g., as drawn by electrical engineers when designing a circuit at the transistor level of detail).
FIGS. 1
b
and
1
c
show how the transistor
101
a
of
FIG. 1
a
may be constructed with specific metal traces (amongst other features) that are formed over or upon the surface of semiconductor material.
Referring to
FIG. 1
a
(which shows a specific type of transistor referred to as an N type Metal Oxide Semiconductor Field Effect Transistor (MOSFET)), note that a transistor typically has three nodes
102
a
,
103
a
,
104
a
. Generally, one node is used to help control whether or not (and if so, how much) current is allowed to flow between the other two nodes. Accordingly, node
102
a
(which is often referred to as a “gate” node) corresponds to the first node described above; and, nodes
103
a
and
104
a
correspond to the other two nodes described above (which are often referred to as the “drain” and “source” nodes, respectively)
The transistor
101
a
of
FIG. 1
a
is designed from the perspective that current is designed to flow “into the drain” node
103
a
and “out of the source” node
104
a
. Thus, current flow
110
corresponds to a typical flow of current that may pass through transistor
101
a
. Here, as electrical current corresponds to a “flow” of electrons (which may be viewed, to some extent, as behaving similar to a flow of water); and, as electrons are negatively charged, current flow (in terms of a flow of positive charge) is opposite in direction to the flow of electrons. Thus, when current is flowing “into” the drain node
103
a
and “out of ” the source node
104
a
as depicted by current flow
110
; in actuality, electrons are flowing from the source node
104
a
to the drain node
103
a
according to electron flow
111
.
Here, the terminology used for the transistor nodes are readily understandable if the transistor is analogized to a kitchen sink. That is, the transistor has a “source” of electrons from which electrons flow into the transistor (e.g., like a faucet acts as a source of water that flows into a sink), a “drain” that collects the flow of electrons to remove electrons from the transistor (e.g., like a drain that acts to empty the flow of water from a sink); and, a “gate” for controlling the magnitude of the electron flow (i.e, the amount of current) (e.g., as the position of a water faucet handle or knob controls the flow of water into a sink). Generally, the magnitude and polarity of voltage applied to the gate node
102
a
(with respect to the source node
104
a
) determines the magnitude of electron flow for the transistor
101
a
if its current flow
110
is not otherwise constrained or controlled (e.g., by other transistors to which transistor
101
a
is coupled).
FIGS. 1
b
and
1
c
describe how the transistor
101
a
of
FIG. 1
a
can be manufactured over/upon an area of semiconductor material according to two different topological perspectives. Here,
FIG. 1
b
corresponds to a “top view” of a transistor (i.e., looking down over a the semiconductor surface
105
b
); while,
FIG. 1
c
corresponds to a “cross section” of a transistor (i.e., looked at from the side of the transistor itself.). Referring to both
FIGS. 1
b
and
1
c
, the source node
104
a
of
FIG. 1
a
is constructed with source wiring
104
b
,
104
c
; the drain node
103
a
is constructed with drain wiring
103
b
and drain contact
107
b
,
107
c
; and the gate node
102
a
of
FIG. 1
a
is constructed with gate wiring
102
b
1
,
102
c
1
, gate via
106
b
,
106
c
, and gate structure
102
b
2
and
102
c
2
. Note that, as a characteristic of MOS devices (Referring to
FIG. 1
c
), a layer of oxide
112
c
resides between the gate structure
102
c
2
and the semiconductor material
105
c.
If electrons are to flow according to the electron flow
111
observed in
FIG. 1
a
, referring now to
FIG. 1
b
and
1
c
, electrons will flow from source wiring fingers
104
b
1
and
104
b
2
. Here, electrons will flow within diffusion region
108
b
: 1) from source wiring finger
104
b
1
beneath gate finger
102
b
2
a
to drain contact
107
b
,
107
c
(i.e., in the +x direction); and, 2) from source wiring finger
102
b
2
a
beneath gate finger
104
b
2
b
toward drain contact
107
b
,
107
c
(i.e., in the −x direction). The diffusion region
108
b
(and
108
c
of
FIG. 1
c
) is a conducting region of the semiconductor surface
105
b
that is more conducting that the surrounding semiconductor surface area outside the diffusion region.
The diffusion region
108
b
,
108
c
is typically formed by implanting “dopant” or “impurity” atoms (e.g., Boron (B), Phosphorous (P)) into the semiconductor surface so as to improve its electrical conductivity (e.g., which, in effect, converts the “semi-conductor” to a material that is more akin to a “conductor” within the diffusion region
108
b
,
108
c
). The formation of a diffusion region
108
b
,
108
c
helps keep transistors isolated from one another by limiting their conducting regions to specified regions within the semiconductor material. The diffusion region
108
b
,
108
c
is also frequently referred to as an “active region”, “an active device region”, “an implant region” and the like.
Note that two different paths are created for the transistor's “source-to-drain” electron flow
111
. The use of two different paths effectively allows the transistor to be “packed” into a dense structure which provides, in turn, additional space on the semiconductor surface
105
b
(e.g., where additional transistors may be formed). As such, the use of two different electron flow paths tends to optimize the efficiency of the semiconductor surface area that is consumed by the transistor devices formed thereon. Continuing then with a discussion of electron flow through the transistor, once electrons reach the drain contact (from either direction) they flow “up” the drain contact
107
b
,
107
c
(i.e., in the +z direction) and then along drain wiring
103
b
,
103
c
(along the x axis).
Note that the amount of electrons available for flow (e.g., which is directly related to the amount of current flow through the transistor) is largely controlled by the voltage established between the gate fingers
102
b
2
a
and
102
b
2
b
and their respective source fingers
104
b
1
and
104
b
2
(i.e., the voltage between fingers
102
b
2
a
and
104
b
1
helps determine the electron amount that flows in the +x direction; and, the voltage between fingers
102
b
2
a
and
104
b
2
helps determine the electron amount that flows in the −x direction). Such a voltage, when applied along gate wiring
102
b
1
, should appear along the entire gate structure
102
b
2
(including gate fingers
102
b
2
a
and
102
b
2
b
) because of the electrical conductivity provided by gate via
106
b
,
106
c
).
Given this

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