Method and apparatus for automated synthesis of...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C375S349000

Reexamination Certificate

active

07640519

ABSTRACT:
Methods and apparatuses to automatically generate time multiplexed multi-channel circuits from single-channel circuits. At least one embodiment of the present invention automatically and efficiently synthesize multi-channel hardware for time-multiplexed resource sharing by automatically generating a time multiplexed design of multi-channel circuits from the design of a single-channel circuit. Channel specific elements of the single-channel design (e.g., registers and memories) are replaced with corresponding elements of N-times more capacity for pipelining the signal processing for multiple channels.

REFERENCES:
patent: 5745837 (1998-04-01), Fuhrmann
patent: 7145972 (2006-12-01), Kumar et al.
patent: 2003/0135716 (2003-07-01), Vinitzky
patent: 2006/0149927 (2006-07-01), Dagan et al.
patent: 2007/0005942 (2007-01-01), Vinitzky et al.
patent: PCT/IL2006/000280 (2006-09-01), None
Habinc, Sandi “Functional Triple Modular Redundancy (FTMR)” Design and Assessment Report, pp. 1-56. European Space Agency Contract Report, Gaisler Research, Sweden, FPGA-003-01 Version 0.2 Dec. 2002 www.gaisler.com.
Lyons, R.E.; Vanderkulk, W.; “The Use of Triple-Modular Redundancy to Improve Computer Reliability” pp. 200-209. Apr. 1962, IBM Journal.
Weaver, Nicholas; Markovskiy, Yury; Patel, Yatish; Wawrzynek, John; “Post-Placement C-Slow Retiming for the Xilinx Virtex FPGA” 10 pages. Copyright 2003 ACM 1-58113-651—X/03/0002 FPGA '03, Feb. 23-25, Monterey, California USA.
Notification to Pay Additional Fees for International Application No. PCT/US2004/010006, mailed Jun. 23, 2005, 8 pages. European Patent Office, Rijswijk. Authorized Officer: Iveta Bujanska.
Shalash, Ahmad F., et al., “Power Efficient Fir Folding Transformation For Wireline Digital Communications”, Copyright 1998 IEEE, 0-7803-5148-7/98, pp. 1816-1820.
Sundararajan, Vijay, et al., “Synthesis of Low Power Folded Programmable Coefficient Fir Digital Filters”, Copyright 2000, IEEE, 0-7803-5973-9/00, pp. 153-156.
Lin, John, et al., “A New Multi-Algorithm Multichannel Cascadable Digital Filter Processor”, IEEE 1988 Custom Integrated Circuits Conference, CH2584-1/88/0000-0060. Copyright 1988 IEEE. pp. 10.7.1-10.7.5.
Hassoun, Soha, et al., “Architectural Retiming: Pipelining Latency-Constrained Circuits” Copyright 1996 ACM, Inc. 0-89791-833-9/96/0006, pp. 708-713. 33rdDesign Automation Conference. XP-002330653.
Parhi, Keshab K., et al, “Synthesis of Control Circuits in Folded Pipeline DSP Architectures”, Copyright 1992 IEEE, 0018-9200/92503.00 vol. 27, No. 1, Jan. 1992. pp. 29-43.
PCT Notification Of Transmittal Of The International Search Report And The Written Opinion Of The International Searching Authority, Or The Declaration, for PCT International Appln No. US2004/010006, mailed Sep. 2, 2005, (17 pages total).
James E. Thornton: “Parallel Operation in the Control Data 6600”,AFIPS Proc. FJCC, pt. 2 vol. 26, pp. 33-40, 1964.
Eran Halperin; Uri Zwick: “Combinatorial Approximation Algorithms for the Maximum Directed Cut Problem”, Proceedings of 12th Symposium on Discrete Algorithms, pp. 1-7, 2001.
Keshab K. Parhi: “VLSI digital signal processing systems: design and implementation”, Wiley-Interscience, pp. 91-118 & 149-187, 1999.
Jhon J. Leon Franco; Miguel A. Melgarejo: “FPGA Implementation of a Serial Organized DA Multichannel FIR Filter”,Tenth ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, Feb. 24-26, 2002.
U.S. Appl. No. 60/429,014, filed Nov. 26, 2002, 48pgs.

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