Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-31
2007-07-31
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10856280
ABSTRACT:
Methods and apparatuses to automatically modify a circuit design according to the possible deviation in the subsequent implementation of the circuit. In one aspect, a method to design a circuit includes: determining whether a design constraint is likely to be violated during a subsequent routing implementation of a design of the circuit; and, modifying the design of the circuit to reduce likelihood of the design constraint being violated during a subsequent implementation. For example, a route for a net with a number of fanout larger than two and on a timing critical or near-critical path may be considered sensitive to route topology such that an alternative routing path may lead to a violation in timing constraint; to reduce the possibility of a timing problem in a subsequent routing solution, a transformation can be selectively applied to the circuit design to an extent not worsening a cost function.
REFERENCES:
patent: 5666290 (1997-09-01), Li et al.
patent: 5696771 (1997-12-01), Beausang et al.
patent: 5787008 (1998-07-01), Pullela et al.
patent: 5978572 (1999-11-01), Toyonaga et al.
patent: 6009248 (1999-12-01), Sato et al.
patent: 6543036 (2003-04-01), Iyer et al.
patent: 6553338 (2003-04-01), Buch et al.
patent: 2003/0051217 (2003-03-01), Cheng
patent: 2004/0016842 (2004-01-01), Couchey
patent: 2004/0017207 (2004-01-01), Herrmann et al.
Changfan, Chieh et al. “Timing Optimization on Routed Designs with Incremental Placement and Routing Characterization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 19, No. 2 (Feb. 2000), pp. 188-196.
Kastner, Ryan et al. “Predictable Routing,” IEEE/ACM International Conference on Computer-Aided Design (Nov. 5, 2000), pp. 110-113.
Ren, Pan and Kung. “Sensitivity Guided Net Weighting for Placement Driven Synthesis,” ISPD'04 (Apr. 18-21, 2004), pp. 10-17.
Coudert O: “Timing and design closure in physical design flows”, Proceedings of the International Symposium on Quality Electronic Design, Mar. 18, 2002 (6 pages).
Phillip Christie, et al., “Prelayout Interconnect Yield Prediction”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 1, Feb. 2003, 6pp.
Crews Andrew
McElvain Kenneth S.
Ramachandran Champaka
Blakely , Sokoloff, Taylor & Zafman LLP
Lin Sun James
Synplicity, Inc.
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