Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1997-08-22
2000-12-12
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711152, 711168, 711151, G06F 1200
Patent
active
061611697
ABSTRACT:
A method, apparatus, and article of manufacture for asynchronously writing and reading multiple data streams is disclosed. The method comprises the steps of writing a plurality of data sub-streams into shared memory buffers asynchronously and in parallel using a write process for each data stream, reading the plurality of data sub-streams from the shared memory buffers asynchronously and in parallel using a read process for each data sub-stream, and writing the data sub-stream into the storage device. Data passing between the write processes and the read processes are stored in a plurality of shared memory buffers, with access to the shared memory buffers controlled by semaphores. The semaphores are used to write-block a shared memory buffer to render the buffer inaccessible to other write processes, to write-unblock a next available shared memory buffer to render it available to a next write process, to read-block the shared memory buffer, to write the data sub-stream to the shared memory buffer, and to read-unblock the shared memory buffer. This allows the bandwidth of the storage devices to be more fully utilized, and improves I/O throughput. The apparatus comprises a system for performing these operations, and the article of manufacture comprises a computer-readable program storage medium tangibly embodying the above method steps.
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Bataille Pierre-Michel
Cabeca John W.
NCR Corporation
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