Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-04-29
2004-03-16
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S083000, C326S112000
Reexamination Certificate
active
06707317
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the design of digital circuits that operate asynchronously. More specifically, the present invention relates to a method and an apparatus for asynchronously controlling domino logic circuits.
2. Related Art
Domino logic circuits are becoming increasingly popular because they provide reduced input capacitance and low switching thresholds, which results in increased speed. Moreover, the use of domino logic leads to simple, area-efficient circuit layouts, which save space on a semiconductor die.
Referring to
FIG. 1A
, a domino logic circuit operates by first entering a precharging state that precharges an interior node
105
to a high voltage. This precharging operation is accomplished by using P-type transistor
107
to pull interior node
105
to a high voltage. Note that this precharging operation sets the output
106
of inverter
103
to a low voltage. During a subsequent evaluation state, interior node
105
either switches from the high voltage to a low voltage, or remains at the high voltage depending upon the inputs
102
and
104
and the function implemented by transistors in functional circuitry
112
.
When interior node
105
falls during the evaluation state, it causes the output
106
of inverter
103
to change, which can cause outputs of a chain of downstream domino logic stages to change in the same way as a chain of dominos falls.
In a synchronous system, it is a relatively simple matter to synchronize the precharging and evaluation operations with different phases of a system clock signal. However, in an asynchronous system, which does not operate with reference to a system clock, coordinating the precharging and evaluation operations can be considerably more challenging.
Note that although asynchronous circuits provide a number of design challenges, asynchronous circuits are free from having to continually synchronize with a system clock signal. This allows asynchronous circuits to run at significantly higher speeds.
Hence, what is needed is a method and an apparatus for controlling the sequencing of precharging and evaluation operations for a domino logic circuit in an asynchronous manner without having to refer to a system clock signal.
SUMMARY
One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit includes a number of stages, including a present stage that receives one or more inputs from a prior stage and generates one or more outputs for a next stage. It also includes a control circuit that ensures that the present stage enters a precharging state before entering a subsequent evaluation state in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit receives a prior control signal from the prior stage and sends a present control signal to the next stage.
In a variation on this embodiment, the prior control signal indicates that the prior stage is in an evaluation state in which the prior stage generates at least one output for the present stage. Upon receiving the prior control signal, the control circuit for the present stage is configured to set a present control signal so that domino logic within the present stage enters the evaluation state. This causes domino logic within the present stage to evaluate at least one input received from the prior stage to produce at least one output for the next stage. The control circuit also resets the prior control signal, so that domino logic within the prior stage returns to a precharging state. In this way, domino logic within the prior stage precharges before entering a subsequent evaluation state.
In a variation on this embodiment, if at least two stages follow the present stage, the present stage is configured to wait to enter the evaluation state until a feedback signal is received from a stage following the next stage. This feedback signal indicates that the stage following the next stage has entered an evaluation state, which causes the next stage to enter the precharging state. In this way, the next stage precharges before entering a subsequent evaluation state.
In a variation on this embodiment, a keeper circuit is configured to maintain an existing value on an output of the present stage while the present stage enters the evaluation state.
In a variation on this embodiment, domino logic circuitry for the present stage includes: a pulldown transistor for pulling an internal node of the present stage to a low voltage during the evaluation state; and a pullup transistor for pulling the internal node of the present stage to a precharge voltage during the precharging state.
In a variation on this embodiment, the control circuit for the present stage is implemented using a GasP module. This GasP module fires when all its inputs are set. Upon firing, the GasP module sets all of its outputs and resets all of its inputs. (The design of a GasP module is described in more detail below with reference to
FIGS. 6-8D
.)
In a variation on this embodiment, a first stage receives one or more inputs from circuitry that does not contain domino logic. In this variation, a control circuit for the first stage causes the first stage to automatically leave the evaluation state after a fixed period of time to enter a hold state. During this hold state, inputs to the first stage cannot corrupt data within domino logic in the first stage.
In a variation on this embodiment, the cycle time between successive evaluation states is six gate delays.
REFERENCES:
patent: 6356117 (2002-03-01), Sutherland et al.
patent: 6590424 (2003-07-01), Singh et al.
Ebergen Josephus C.
Gainsley Jonathan
Lexau Jon
Sutherland Ivan E.
Chang Daniel
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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