Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2002-07-23
2004-03-02
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S082000, C326S095000, C326S112000
Reexamination Certificate
active
06700410
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the design of digital circuits that operate asynchronously. More specifically, the present invention relates to a method and an apparatus for asynchronously controlling a high-capacity domino pipeline in a manner that maximizes throughput.
2. Related Art
Domino logic circuits are becoming increasingly popular because they provide reduced input capacitance and low switching thresholds, which result in increased speed. Moreover, the use of domino logic leads to simple, area-efficient circuit layouts, which save space on a semiconductor die.
Referring to
FIG. 1A
, a domino logic circuit operates by first entering a precharging state that precharges an interior node
105
to a high voltage. This precharging operation is accomplished by using P-type transistor
107
to pull interior node
105
to a high voltage. Note that this precharging operation sets the output
106
of inverter
103
to a low voltage. During a subsequent evaluation state, interior node
105
either switches from the high voltage to a low voltage, or remains at the high voltage depending upon the inputs
102
and
104
and the function implemented by transistors in functional circuitry
112
.
When interior node
105
falls during the evaluation state, it causes the output
106
of inverter
103
to change, which can cause outputs of a chain of downstream domino logic stages to change in much the same way as a chain of dominos falls.
In a synchronous system, it is a relatively simple matter to synchronize the precharging and evaluation operations with different phases of a system clock signal. However, in an asynchronous system, which does not operate with reference to a system clock, coordinating the precharging and evaluation operations can be considerably more challenging.
In spite of the fact that asynchronous circuits present a number of design challenges, asynchronous circuits are free from having to continually synchronize with a system clock signal. This allows asynchronous circuits to run at significantly higher speeds.
Singh and Nowick describe an asynchronous control circuit for a high-capacity domino pipeline that can accommodate one data item per pipeline stage (see “Fine-Grain Pipelined Asynchronous Address for High-Speed DSP Applications,” Proceedings of the IEEE Computer Society Annual Workshop on VLSI, Apr. 27-28, 2000 Orlando, Fla.). This asynchronous control circuit has a minimum cycle time between successive evaluation operations of at least eight gate delays, which is not optimal. Moreover, the control circuit described by Singh and Nowick consumes a large amount of energy.
What is needed is a method and an apparatus for asynchronously controlling a domino logic pipeline with a faster cycle time and lower energy consumption than the circuit described by Singh and Nowick.
SUMMARY
One embodiment of the present invention provides a domino logic circuit that operates asynchronously. This domino logic circuit contains a pipeline comprised of a number of stages of domino logic, including a present stage that receives one or more inputs from a prior stage and that generates one or more outputs for a next stage. The present stage includes a control circuit that is configured to ensure that the present stage enters a precharging state before entering an evaluation—in which one or more inputs of the present stage are used to generate one or more outputs. This control circuit operates by receiving a prior control signal from the prior stage and sending a present control signal to the next stage. During this process, the control circuit ensures that a minimum cycle time between successive evaluation states is six gate delays.
In a variation on this embodiment, upon receiving the prior control signal from the prior stage indicating that the prior stage is in the evaluation state, the control circuit for the present stage causes domino logic within the present stage to enter the evaluation state, so that the domino logic within the present stage evaluates at least one input received from the prior stage to produce at least one output for the next stage. The control circuit also causes the domino logic within the prior stage to return to the precharging state. This allows the domino logic within the prior stage to precharge before entering a subsequent evaluation state.
In a variation on this embodiment, the control circuit for the present stage includes a GasP module. This GasP module fires when all of its inputs are set. This firing causes all outputs of the GasP module to be set and causes all inputs to the GasP module to be reset. (The design of a GasP module is described in more detail below with reference to
FIGS. 7-9
.)
In a variation on this embodiment, the control circuit for the present stage feeds an evaluation signal into domino logic in the present stage, which causes the domino logic in the present stage to enter the evaluation state. The control circuit for the present stage also feeds a precharging signal into the present stage, which causes the domino logic in the present stage to enter the precharging state. If the evaluation signal and the precharging signal are not asserted, the domino logic in the present stage enters a hold state in which the outputs of the domino logic do not change.
In a further variation, the control circuit for the present stage includes a first GasP module that generates the evaluation signal for the present stage, and a second GasP module that generates the precharging signal for the present stage. In this variation, the first GasP module receives an input from the second GasP module and an input from the control circuit for the prior stage. Furthermore, the second GasP module receives an input from the control circuit for the next stage.
In a further variation, the control circuit for the present stage includes a GasP module that generates the evaluation signal for the present stage. In this variation, the precharging signal for the present stage is generated from the evaluation signal for the next stage.
In a variation on this embodiment, the present stage includes a keeper circuit that maintains an existing value on an output of the present stage.
In a variation on this embodiment, the domino logic for the present stage includes a pulldown transistor for pulling an internal node of the present stage to a low voltage during the evaluation state. It also includes a pullup transistor for pulling the internal node of the present stage to a precharge voltage during the precharging state.
REFERENCES:
patent: 6356117 (2002-03-01), Sutherland et al.
patent: 6590424 (2003-07-01), Singh et al.
Publication entitled “Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications,” by Montek Singh et al., IEEE Computer Society Annual Workshop on VLSI, Apr. 27-28, 2000, Orlando, Florida.
Publication entitled “An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz,” by Montek Singh et al., Proceedings of IEEE ASYNC 2002, pp. 84-95.
Chang Daniel
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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