Method and apparatus for asymmetric/symmetric DRAM detection

Details Method and apparatus for asymmetric/symmetric DRAM detection Method and apparatus for asymmetric/symmetric DRAM detection

1996-02-09

1998-09-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711 4, 711 5, 711 15, 36518905, 36523002, 36523006, G06F 1202

Patent

active

058026037

ABSTRACT:
A method and apparatus for detecting DRAM symmetry. A memory address including a row address and a column address bit is forced to a known value regardless of the host bit which would otherwise be mapped thereto. If the forced bit is in the column address it should be a bit which is not used by an asymmetric DRAM of the depth in the system to be tested, but would be used in a symmetric DRAM of the same depth. Conversely, if the forced bit is in the row address the bit should be used in the asymmetric case but not in the symmetric case. It is important that regardless of what bit in the memory address is forced, the forced bit should not be used by both cases at the depth tested. A first and second known value, are written respectively to two memory addresses which differ only in the value which would normally be mapped to this forced bit. The forced bit will cause an overwrite if the DRAM is of the type which uses the forced bit in its addressing. Thus, by reading the potentially overwritten address, symmetry is determined.

REFERENCES:
patent: 5265218 (1993-11-01), Testa et al.
patent: 5278801 (1994-01-01), Dresser et al.
patent: 5386383 (1995-01-01), Raghavachari
patent: 5600604 (1997-02-01), Chen

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