Method and apparatus for associating an error in a layout...

Details Method and apparatus for associating an error in a layout... Method and apparatus for associating an error in a layout...

2007-12-25

2007-12-25

Do, Thuan V. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11159285

ABSTRACT:
One embodiment of the present invention provides a system that associates an error in a layout with a cell. During operation, the system receives a layout which is designed to create a target feature with an intended shape. Next, the system determines an error in a critical dimension of the target feature. The system then identifies a cell in the layout based on the error's location in the layout, thereby associating the error with the cell. Note that associating errors with cells allows the errors to be summarized based on the associated cells, which can reduce the amount of time required to identify and fix the errors.

REFERENCES:
patent: 6374395 (2002-04-01), Wang
patent: 6571374 (2003-05-01), Runyon et al.
patent: 2003/0121019 (2003-06-01), Brown et al.
patent: 2006/0053400 (2006-03-01), Meyer et al.
patent: 2006/0090146 (2006-04-01), LeBritton et al.
patent: 2006/0236271 (2006-10-01), Zach

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