Method and apparatus for assigning thread priority in a...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble

Reexamination Certificate

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C712S228000, C718S103000, C718S108000

Reexamination Certificate

active

07454600

ABSTRACT:
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

REFERENCES:
patent: 6404161 (2002-06-01), Roubinet et al.
patent: 6542921 (2003-04-01), Sager
patent: 6606639 (2003-08-01), Jacobson et al.
patent: 2002/0138670 (2002-09-01), Johnson
patent: 0 488 501 (1991-09-01), None
patent: WO 99/21082 (1998-10-01), None
patent: WO 01/04750 (2000-06-01), None
Susan J. Eggers et al., Simultaneous Multithreading: A Platform for Next-Generation Processors, Sep./Oct. 1997, IEEE Micro, pp. 12-19.
David W. Burns, Pre-Silicon Validation of Pentium4's SMT Capabilities, Intel Design and Test Technology Conference, pp. 1-5, no known publication date.

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