Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-06-30
2002-11-26
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06487710
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to assigning signal routes in a programmable logic device (PLD), and more particularly to assigning signal routes to input signals requiring different voltage standards.
BACKGROUND
Example complex programmable logic devices (CPLD) are found in the XC9500 family of CPLDs from Xilinx. The XC9500 CPLDs include input/output blocks (IOBs), function blocks (FBs), and a switch matrix for interconnecting the function blocks and I/O blocks. Such a switch matrix is described in U.S. Pat. No. 5,563,528, entitled, Multiplexer for Programmable Logic Device, to Diba et al, which is incorporated herein by reference. The inputs to the switch matrix are input pins from the IOBs and feedback inputs from the FBs.
The semiconductor industry standard operating voltage has in the past been 5 volts, and all devices on a system board have operated at 5 volts. The IOBs were designed to interface with structures outside the chip using 5 volts as a power supply voltage. However, the industry is presently migrating to lower voltages for faster operation at lower power. Rather than all chips in a system operating at a single voltage, different chips operating at different power supply voltages may be present in a single system. It may be desirable for a CPLD in a mixed-voltage system to interface with chips operating at different voltage levels.
Some devices in the XC9500 family of CPLDs have multiple input banks. An input bank is a set of input pins that are controlled by the same input voltage level (V
ref
). All the pins of a function block belong to the same input bank and are all controlled by the same V
ref
. Each input bank is programmable to support a selected V
ref
. By setting the V
ref
of certain input banks to the same voltage level, the banks can be viewed as merged into one bank.
As with any programmable logic device, a CPLD has a limited number of pin resources. Thus, for almost any design, a routing solution that makes efficient use of pin resources while satisfying the input banking requirements is desirable. A method and apparatus that address the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
In various embodiments, methods and apparatus for routing input signals having different voltage requirements in a PLD circuit design are provided by the present invention. The input signals are grouped into logical clusters, wherein the input signals in each logical cluster have a common input voltage standard. Programmable logic elements of the device are grouped into physical clusters, whereby input pins associated with the programmable logic elements are also associated with the physical cluster. Each physical cluster is paired with a logical cluster based on the number of input pins available in the physical cluster and the number of input signals to be routed in the logical cluster. The input voltage standards of the logical clusters are thereby assigned to the paired physical clusters. For each paired logical cluster and physical cluster, the input signals of the logical cluster are routed from the pins of the physical cluster to the programmable logic elements of the physical cluster.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims, which follow.
REFERENCES:
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Jose M. Marquez, “A Hybrid Router for Multiplexer-Based CPLDs”, Jul. 1, 1999, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Egon Balas et al.:“A Parallel Shortest Augmenting Path Algorithm for the Assignment Problem”, 1991, National Science Foundation Grant, pp. 986-1004.
Pierre Kelson, “Fast Parallel Matching in Expander Graphs”, Department of Computer Science University of British Columbia 6356 Agricultural Road, Vancouver, B.C., Canada, 1993, pp. 293-299.
Constantine N.K. Osiakwan et al: “A Perfect Speedup Parallel Algorithm for the Assignment Problem on Complete Weighted Bipartite Graphs”, Department of Computing and Information Science Queen's University, Kingston, Ontario, Canada, 1990, pp. 293-301.
“The Programmable Logic Data Book 2000”, Virtex 2.5 Field Programmable Gate Arrays, Mar. 9, 2000—Preliminary Product Specification. Available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 4-5.
Scott D. Brown et al.: “Field-Programmable Gate Arrays”, Kluwer Academic Publishers, 1993, pp. 133-145.
Gary Chartrand et al.: “Applied and Algorithmic Graph Theory”, McGraw-Hill, Inc., 1993, pp. 2-3, 5-6, 25-26, 162-167.
Thomas H. Cormen et al.: “Introduction to Algorithms”, the MIT Press, Cambridge MA, 1991, Chapter 27, pp. 600-602.
Cartier Lois D.
Dinh Paul
Maunu LeRoy D.
Smith Matthew
Xilinx , Inc.
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