Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-02
2004-05-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06738959
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the process of routing signals between circuit elements within an integrated circuit. More specifically, the present invention relates to a method and an apparatus for assigning nets that carry signals between circuit elements to specific metal layers during the process of routing of signals between circuit elements within an integrated circuit.
2. Related Art
Dramatic advances in integrated circuit technology presently make it possible to integrate hundreds of millions of transistors onto a single semiconductor chip. These dramatic advances are made possible by improvements in wafer processing technology and by automated design tools, which can handle the complexity involved in designing circuits with hundreds of millions of transistors.
These automated design tools operate by receiving a functional specification of an integrated circuit and then decomposing the functional specification into corresponding circuit elements. These circuit elements are then placed at specific locations on the semiconductor chip. During a subsequent routing operation, various nets are routed to form signal pathways between the circuit elements. A timing model can subsequently be used to calculate path delays through the nets to verify that the circuit meets timing constraints. These path delays can be adjusted, if necessary, by assigning nets to metal layers with different delay characteristics. Also, flip-flops can be inserted into nets that do not meet minimum timing requirements. Since inserting flip-flops changes the logic of the circuit, a design engineer typically performs this step manually before repeating the placement and routing operations.
One routing technique operates by assigning nets to groups associated with specific metal layers according to an engineer's estimate of the speed of particular nets. However, this technique is not ideal because it requires the engineer to manually assign nets to metal layers on an ad hoc basis, without providing the engineer with a clear set of alignment rules.
Hence, what is needed is a method and an apparatus for assigning nets to specific metal layers during the process of routing of signals between circuit elements without the drawbacks described above.
SUMMARY
One embodiment of the present invention provides a system that facilitates routing nets between cells in a circuit layout. During operation, the system receives a circuit design to be routed, wherein the circuit design includes multiple circuit blocks that have been placed at specific locations within the circuit layout. Next, the system determines estimated lengths for nets that couple these circuit blocks together. The system then calculates the delay for the nets that couple the circuit blocks using a class one rule. If the delay in a given net is greater than a specified delay, the system inserts a virtual repeater into the given net to decrease the delay.
In a variation of this embodiment, determining estimated lengths for nets involves computing a Steiner tree.
In a further variation, determining the estimated lengths for the nets involves assigning nets to layers.
In a further variation, the class one rule assigns the given net to a first through fourth metal layer.
In a further variation, if the delay is less than one clock cycle, the system assigns the given net to a first group.
In a further variation, if the delay is not less than one clock cycle the system calculates the delay for the nets using a class two rule, and if the delay in the given net is greater than a specified delay, the system inserts a virtual repeater in the given net to decrease the delay.
In a further variation, the class two rule assigns the given net to a fifth through sixth metal layer.
In a further variation, if the delay is less than one clock cycle, the system assigns the given net to a second group.
In a further variation, if the delay is not less than one clock cycle the system calculates the delay for nets using a class three rule and if the delay in the given net is greater than a specified delay, the system inserts a virtual repeater in the given net to decrease the delay.
In a further variation, the class three rule assigns the given net to a seventh through eighth metal layer.
In a further variation, if the delay is less than one clock cycle, the system assigns the given net to a third group.
In a further variation, the system reports the first group, the second group, and the third group to provide a starting assignment for a subsequent routing process.
In a further variation, if the delay is not less than one clock cycle, the system inserts a virtual flip-flop in the given net, and changes the delay criterion from greater than one clock cycle to greater than two clock cycles. The system then repeats the process.
REFERENCES:
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5996735 (1999-12-01), Perritt et al.
patent: 6043677 (2000-03-01), Albu et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6557145 (2003-04-01), Boyle et al.
Cho Seong Rai
Jung Dae Suk
Pai Yet-Ping
Grundler Edward J.
Lee, Jr. Granville D.
Smith Matthew
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