Method and apparatus for asserting a hardware pin to disable...

Details Method and apparatus for asserting a hardware pin to disable... Method and apparatus for asserting a hardware pin to disable...

2007-01-24

2010-06-01

Suryawanshi, Suresh K (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S323000

Reexamination Certificate

active

07730337

ABSTRACT:
A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.

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patent: 2006/0168460 (2006-07-01), Hsiao et al.
patent: 1540539 (2004-10-01), None

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