Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-25
2001-06-12
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S121000, C716S030000, C716S030000
Reexamination Certificate
active
06247166
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits.
DESCRIPTION OF THE RELATED ART
VLSI devices are typically formed as circuit chips having a chip image including multiple logic and memory circuits integrally formed on a single semiconductor substrate. The VLSI devices may be formed, for example, by a field effect transistor (FET) technique with conventional complementary metal oxide semiconductor (CMOS) technology. Advancement in VLSI technology allows system architects to pack more and more functions into a chip.
Predesigned functional macros or leaf cells may include many different integrated circuits of varying complexity. Leaf cells are comprised of hand generated schematics, symbols, and physicals or layouts. As used in the following description and claims, physicals and layouts are equivalent terms. For example leaf cells include simple inverter circuits, multiplexor (MUX) circuits, and empty pad or spacing circuits. Custom arrays are typically designed individually and may include thousands of leaf cells. This design approach creates serious problems in the layout and design of the overall chip image because the conventional design approach does not effectively facilitate placement and wiring of multiple leaf cells on the chip to provide a desired system.
Assembly of array and datapath macros is a tedious and error prone procedure, especially when attributes and/or properties for Layout Versus Schematic (LVS) are required. These macros typically have thousands of leaf cells that need to be assembled. Standard assembly procedures such a Place and Route programs are too random and complicated for the structured assembly required for some problems, such as memory array and datapath macros. Known array generation or grow programs are too constrained and rigid for general application.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an improved method and apparatus for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits. Other important objects of the present invention are to provide such method and apparatus for assembling array and datapath macros for very large scale integrated (VLSI) semiconductor integrated circuits substantially without negative effects and that overcome some disadvantages of prior art arrangements.
In brief, a method, computer program product and apparatus for assembling array and datapath macros are provided for very large scale integrated (VLSI) semiconductor integrated circuits. User selections are received for a hierarchical macro to be created. The user selections include a command list of multiple leaf cell build commands. X and Y placer pointers are initialized. A next build command is obtained from the command list and a command type is identified. Responsive to identifying a next leaf cell build command in a leaf cell group, a user selected schematic or physical view is identified. A corresponding leaf cell view is read for the user selected schematic or physical view. X and Y sizes are obtained for the leaf cell view. Then the leaf cell is oriented and placed. Next X and Y placer pointers are calculated and the sequential steps are repeated until a last leaf cell build command in the leaf cell group is found. Then the sequential steps return to obtain a next build command from the command list.
Connections to adjacent leaf cells are provided by abutting cells together. Port and pin connections from the periphery of the array of placed leaf cells are propagated to a next hierarchical level of the hierarchical macro being created.
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Aipperspach Anthony Gus
Freiburger Peter Thomas
International Business Machines - Corporation
Pennington Joan
Smith Matthew
Thompson A. M.
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