Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
1999-05-20
2001-12-04
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S710000
Reexamination Certificate
active
06327680
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to arrays for storing data or other information, and more particularly to the repair of defective array cells.
2. Related Art
Modern electronic devices store data in a variety of places. For example, the typical main data memory for a computer system may have a variety of DIMMS (dual in line memory modules) or SIMMS (single in line memory modules) for storing data. Many computer systems have a data cache associated with each processor, also storing data in arrays. Various buffers and bridges throughout a computer system contain arrays for storing data such as DMA (direct memory access) devices or buffers between busses of different speeds or widths. Many peripheral devices, both on and off the system board, use arrays to store data.
Structure of Arrays
Arrays consist of memory locations arranged in rows and columns. Even when an array is not physically structured in rows and columns, the individual locations within the array may be addressed by a row address and a column address. For example, a memory protocol may receive an address across a very wide address bus, and divide the memory address into a row portion and a column portion for delivery to a particular memory array. Thus, many systems address memory locations within an array by a row address and a column address. Moreover, such systems typically use a very large number of arrays using such two-coordinate addressing schemes.
Structure of Defects
Unfortunately, during the manufacturing or other processes, memory arrays can contain defective locations. A defective location may have a “stuck at” fault, at which the memory location cannot be modified. Other faults, such as a “stuck to” fault are also found. “Stuck to” faults connect a memory location to an adjacent memory location, such that the faulty memory location always contains whatever data has been stored in the adjacent memory location and cannot be used independently. Many other faults will be apparent to anyone skilled in the art who has spent time working with arrays for storing data.
Frequency of Defects
As arrays become increasingly larger on processor chips, the percentage of manufacturing defects related to arrays also increases.
Overview of Array Repair
The process of determining how to repair defective cells in an array usually includes the following steps. The first step is to determine which bit cells are faulty by running an array built-in self test (ABIST). The second step is to determine if the array is repairable using spare cells. The number of spare cells may not be adequate to repair all array faults.
Structure of ABIST
Defective bits are normally encountered through an array built in self test (ABIST) process. ABIST engines create data and attempt to store the data in the memory array, and then attempt to read the data. If the data cannot be read, then a fail has been detected. ABIST engines detect the fail by comparing the data that is actually contained in the array location with an expected data value generated by the ABIST engines itself.
Structure of Redundancy
One of the common methods of correcting faults in a memory array is to provide row and column redundancy. Redundancy is provided by adding additional rows or columns to an array. When a defective bit within defective memory location is discovered in an array, thereafter all addresses to the row or column containing the fail are redirected to the replacement row or column.
There are two types of redundancy mechanisms that can be used. The first type is word line redundancy, also known as row replacement, which detects attempts to access a row containing a fail. Row replacement redirects detected accesses to spare row array cells in a replacement row. The second type is column redundancy, also known as column replacement, and detects attempts to access a column containing a fail. Column replacement redirects detected accesses to spare column array cells in a replacement column. Systems can use either type of redundancy mechanism, or both types simultaneously, to repair arrays.
Problems with Redundancy
Unfortunately, space limitations often limit the number of available replacement rows and columns, and assigning these to the various defective bits can easily be done suboptimally. For any given fail, either row replacement or column replacement may be used, and determining which replacement scheme is preferable often requires knowledge of other defective bits in the array.
For example, assigning a replacement column (thereby selecting column repair) might be the more appropriate repair scheme where several defective bits happen to be detected within the same column, since a single replacement column can be used to correct multiple defective bits. On the other hand, if several defective bits are detected in the same row of the array, a replacement row can be used, rather than attempting column repair on any of the detected defective bits.
Problems with Using ABIST for Redundancy
Knowledge of other faults, however, may be unavailable when a single fault is discovered. Although ABIST engines are used to detect faults or defective bits in arrays, they do so one fault at a time.
Consequently, present repair hardware or circuits that detect array faults when running ABIST generally do not determine the optimal repair methods for arrays that have both row redundancy and column redundancy.
BRIEF SUMMARY OF THE INVENTION
An apparatus receives a series of locations containing a row address and a column address of a fault detected within an array. A row replacement priority circuit within the apparatus logs the row address of the first fault detected, and thereafter marks a column of any subsequent faults detected in rows other than the row of the first detected fault. Concurrently, a column replacement priority circuit within the apparatus logs the column address of the first fault detected, and thereafter marks a row of any subsequent faults detected in columns other than the column of the first detected fault.
According to one aspect, the present invention includes detection of array defective bits; detection of multibit defective bits, which are individual rows having several defective bits; determination of whether an array is repairable; and where the array is repairable, determination the optimal repair method with a single pass of running ABIST.
REFERENCES:
patent: 4639915 (1987-01-01), Bosse
patent: 5689466 (1997-11-01), Qureshi
patent: 5764655 (1998-06-01), Kirihata et al.
patent: 5795797 (1998-08-01), Chester et al.
Gervais Gilles
Reyes Herman
Bryant Andrea P.
Carvell Robert M.
Chung Phung M.
International Business Machines - Corporation
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