Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-11-16
2003-04-08
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S313000, C710S112000
Reexamination Certificate
active
06546448
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106503, filed Apr. 23, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a computer system using a peripheral component interconnect (PCI) device, and more particularly to PCI bus master and its arbiter with an arbitrating method, in which the PCI master can repeatedly send inquiry signals to a PCI bus after a delay transaction termination is issued on the PCI bus.
2. Description of Related Art
FIG. 1
is a computer system diagram, schematically illustrating a PCI device applied in a computer system. The computer system includes a central processor unit (CPU)
10
. which is coupled to a PCI bus
14
through a host bridge
12
. Several PCI bus masters, such as a graphic adapter
16
a
, an expansion bus bridge
16
b
, a LAN adapter
16
c
for a use of network, a SCSI host bus adapter
16
d
for a use for another smaller computer system, and so on are also coupled to the PCI bus. Each PCI bus master can issue a request signal (RST) to use the PCI bus. A bus arbiter in the host bridge
12
then sends a grant signal (GNT) to the PCI bus master to allow the PCI bus master to use the PCI bus
14
.
The data communication between PCI compatible devices, such as the PCI bus master or a north bridge of a computer chipset, is typically controlled by an interface control signal, which is described in the following. A cycle frame used to indicate a data access action and its duration is typically generated by an initiator, such as the PCI bus master or the north bridge of the computer chipset. As the cycle frame (FRAME) signal is issued, a data transaction through the PCI bus starts. When the cycle frame signal stays at a low logic level, it means that the transaction is performing. At this stage, during an address phase, an address (AD) bus issues a valid address, and simultaneously sends a valid bus command, which satisfies a PCI format, through a command/byte enable (CBE[
3
:
0
]) line so as to instruct the target device to transact data with a data transaction type requested by the initiator. The command/byte enable line includes four bits to have sixteen different commands, each of which has a special purpose and is defined in the PCI bus protocol in detail. After the valid address is issued, the address bus AD sends out the intended data. This period is called a data phase. Simultaneously, immediately after the bus command is issued, a CBE signal with coded commands in the byte is sent out through the CBE line so as to transmit data. As the FRAME signal goes to a high logic level, it means that the last data block of the data transaction is on transmitting status now or the data have been completely transmitted. During read action, an initiator ready (IRDY) signal represents that the initiator is ready for receiving data, and during writing action, a target device ready (TRDY) signal represents that the target device is ready for receiving data. A stop signal is also used to instruct the target device. A STOP signal is used to indicate that the target device requests a stop of data transaction on the initiator.
FIG. 2
is a time waveform sequence, schematically illustrating an operating time sequence during a read action. A bus transaction
20
is defined as a period for use to accomplish a data transaction through the PCI bus. The bus transaction
20
further includes an address phase
22
, and several data phases, such as data phases
24
a
,
24
b
, and
24
c
. Each data phase further includes a wait cycle and a data transfer cycle. For example, the data phase
24
a/b/c
respectively includes a wait cycle
26
a/b/c
and a data transfer cycle
28
a/b/c
. Referring to
FIG. 2
, one can see a read action through the PCI system with related signals described before.
During the first cycle T
1
of a clock (CLK), the initiator issues a FRAME signal to start a data transaction. The AD buss sends a start address so as to select a desired target device, and simultaneously send a byte enable command through the CBE line. This byte enable command remains during all data phases
24
a
,
24
b
, and
24
c
. During the second cycle T
2
, the initiator sends a IRDY signal to indicate the initiator is ready for receiving data. At this moment, the target device is not ready yet so that the wait cycle
26
a
is needed in the data phase
24
a
. The initiator stays at a waiting status during the second cycle T
2
. During the third cycle T
3
, the target device is ready and sends a TRDY signal to indicate its status. The data phrase
24
a
turns to the data transfer cycle
28
a
from the wait cycle
26
a
. The initiator reads data from the target device in the data transfer cycle
28
a
, which extends to a fourth cycle T
4
. During the fourth cycle T
4
, as data is completely read, the target device changes the status of the TRDY and prepares the second data block. At this moment, the data phase
24
b
starts and stays at the wait cycle
26
b
. During a fifth cycle T
5
, the target device sends the TRDY signal again to start a read of the second data block. The initiator read the second data block during the data transfer cycle
28
b
. In case that the initiator cannot read the second data block in time, the initiator send an unready IRDY signal at a sixth cycle T
6
. In this situation, since the TRDY still stays at ready status, the wait cycle
26
c
of the data phase
24
c
is caused by the initiator. During a cycle T
7
, the initiator may be ready again and read the second data block again. The second read block is completely read during a cycle T
8
. Since the FRAME signal has indicated the second data block is the last data block to be ready. The read action stops at the cycle T
8
. Both the IRDY and the TRDY change to unready status. Accordingly, the CBE signal and the AD signal are off.
In this conventional action, only one PCI bus master can use the PCI bus at a bus transaction. So, before performing one of functional devices of a multi-function master, the master should receive a use privilege to use the PCI bus. However, in some simple system, the multiple-function master does not release its use privilege after the data transaction finishes.
FIG. 3
is a system block diagram, schematically illustrating a conventional multi-function master, which is compatible with the PCI bus.
FIG. 4
is a time sequence, schematically illustrating a conventional arbitrating method used by the conventional multi-function master of
FIG. 3
to transmit data.
In
FIG. 3
, there is a PCI bus
40
. A multi-function master
30
is coupled to the PCI bus
40
. The multi-function master
30
includes an arbiter
32
and several functional circuits
34
,
36
, and
38
, in which the arbiter
32
is different from the bus arbiter
31
. The bus arbiter
31
is used to arbitrate all PCI masters (some are not shown) coupled to the PCI bus
40
so as to provide a use privilege to one of the PCI masters. The arbiter
32
is used to arbitrate which one of the functional circuits
34
,
36
, and
38
has a privilege to use the multi-function master
30
. For example, as the multi-function master
30
obtain its use privilege authorized by the arbiter
31
, one of the functional circuits
34
,
36
, and
38
also needs an authorization from the arbiter
32
so as to used the PCI bus
40
.
Some of the functional circuits can be coupled to peripheral apparatus. For example, the functional circuits
34
and
36
are also respectively coupled to a peripheral apparatus
33
and a peripheral apparatus
35
. The functional circuits
34
and
36
include, for example, various interface control circuits, such as a communication interface, a simple I/O interface to match the peripheral apparatuses
33
and
35
. The functional circuit
38
is built in the multi-function master
30
to independently perform its special function, such as a digital signal processor (DSP). Moreover, a peripheral apparatus
42
can also coupled to the arbiter
32
to directly communicate with th
Lai Jiin
Tsai Chau-Chad
Tsai Chi-Che
Yang Chen-Ping
J.C. Patents
Lefkowitz Sumati
Via Technologies Inc.
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