Metal fusion bonding – Process – Preplacing solid filler
Reexamination Certificate
2002-03-27
2004-03-23
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
Preplacing solid filler
Reexamination Certificate
active
06708872
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to soldering, and more particularly, to applying solder to an element on a substrate. The technique is particularly suitable for applying solder columns to bottom surface metallurgy (BSM) pads on a chip career.
2. Description of the Prior Art
Electronic packaging generally contains many levels of packages and interconnections. A first level package may connect one or more silicon chips on a ceramic substrate carrier. A second level package may interconnect one or more such ceramic substrate carriers on an organic board.
The ceramic substrate is connected to the organic board by pins that are typically rigid and made of metal. The rigid pins are brazed on the ceramic substrate with a suitable braze material such as a gold-tin alloy. Ceramic substrates with an array of such pins, i.e., pin grid arrays (PGA), are subsequently plugged into a pin connector or wave soldered to an array of plated through-holes on the organic board. This connection system has disadvantages such as the through-holes limiting the number of wiring channels available in the board. Another disadvantage is the high cost associated with the braze material, the rigid metal pins, and the pin connectors or plated through-holes.
U.S. Pat. No. 4,914,814 to Behun et al. describes how these disadvantages can be avoided by using solder column connection (SCC) technology, which is also known as ceramic column grid array (CCGA) technology. Generally, CCGA technology is less expensive than PGA technology. CCGA technology also provides an improved electrical interconnection that can better withstand stresses associated with thermal expansion mismatch between a ceramic chip carrier and a supporting circuit board.
To connect a ceramic chip carrier to a supporting circuit board using CCGA technology, the chip carrier is soldered to the board using solder columns, which are typically 90% lead and 10% tin. The solder columns are formed and one end is attached to metallized pads on a surface of the ceramic chip carrier. Such pads are provided by a technique known as bottom surface metallurgy (BSM). Then the other end of the solder columns, opposite to the ceramic chip carrier, is attached to the circuit board.
One problem associated with the CCGA assembly process at the module level occurs when the solder columns do not properly join to the metallized pads of the chip carrier BSM surface. The problem occurs when there is a misalignment between the solder columns and the BSM pads. Pitches of 1.27 mm and 1.00 mm between BSM pads, center to center, are conventionally available. For the 1.00 mm pitch, the BSM pads have a diameter of about 0.8 mm with a spacing of about 0.2 mm between adjacent columns. For the 1.27 mm pitch, the BSM pads have a diameter of about 0.86 mm with a spacing of about 0.41 mm between adjacent BSM pads. As such, the aforementioned problem is more pronounced for the 1.00 mm pitch, but it is also apparent with the 1.27 mm pitch. Defects due to misalignment result in a lower product yield, a loss of material and an increased cost due to rework of the CCGA assembly. Another problem is the formation of excess solder, i.e., solder “blobs”, on the chip carrier's BSM surface due to upward force from molten solder during a solder reflow operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved method for applying solder to an element on a substrate, such as a BSM pad on a chip carrier.
It is another object of the present invention to provide such a method that reduces possibility of an excess solder “blob” forming between the elements.
It is a further object of the present invention to provide such a method that utilizes a solder surface tension effect to self-center the solder on the element.
These and other objects of the present invention are achieved by a first method for applying solder to an element on a surface of a substrate, comprising (a) placing a mold over the surface, where the mold includes a conduit that contains the solder, and (b) heating the solder to a molten state so that the solder flows from the conduit onto the element. The conduit enjoys two degrees of horizontal freedom with respect to the surface such that the conduit becomes substantially aligned with the element when the solder is in the molten state.
A second method for applying a solder column to an element on a surface of a chip carrier, comprises (a) securing the chip carrier in a fixture, (b) applying a solution having a first flux concentration onto the element, (c) positioning a mold in the fixture over the chip carrier such that a conduit in the mold is in a preliminary alignment with the element, where the conduit contains the solder column, (d) applying a solution having a second flux concentration onto a end of the solder column remote from the element, where the first flux concentration is greater than the second flux concentration, and (e) heating the solder column to a molten state so that the solder column flows from the conduit onto the element. The conduit enjoys two degrees of horizontal freedom with respect to the chip carrier such that the conduit becomes substantially aligned with the element when the solder column is in the molten state.
A first embodiment of the present invention is an apparatus for applying solder to an element on a surface of a substrate. The apparatus comprises (a) a base for holding the substrate, and (b) a mold that includes a conduit for containing the solder, where the mold is placed on the base over the surface. The conduit enjoys two degrees of horizontal freedom with respect to the surface such that the conduit becomes substantially aligned with the element when the solder is in a molten state.
A second embodiment of the present invention is an apparatus for applying a solder column to an element on a surface of a chip carrier, comprising (a) a base for securing the chip carrier, (b) a mold for positioning on the base over the chip carrier, where the mold includes a conduit that contains the solder, and (c) a weight for placement on the mold to limit vertical freedom of the mold with respect to the surface. The conduit enjoys two degrees of horizontal freedom with respect to the chip carrier such that the conduit becomes substantially aligned with the element when the solder column is in a molten state.
REFERENCES:
patent: 4412642 (1983-11-01), Fisher, Jr.
patent: 4914814 (1990-04-01), Behun et al.
patent: 5244143 (1993-09-01), Ference et al.
patent: 5454159 (1995-10-01), Norell
patent: 5718361 (1998-02-01), Braun et al.
patent: 5718367 (1998-02-01), Covell, II et al.
patent: 6025649 (2000-02-01), DiGiacomo
patent: 6105851 (2000-08-01), Norell et al.
Gruber Peter Alfred
Lei Chon Cheong
Dunn Tom
International Business Machines - Corporation
Johnson Jonathan
Morris Daniel P.
Ohlandt Greeley Ruggiero & Perle L.L.P.
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