Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-29
2009-08-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07574680
ABSTRACT:
Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
REFERENCES:
patent: 5867180 (1999-02-01), Katayama et al.
patent: 6078736 (2000-06-01), Guccione
patent: 6175948 (2001-01-01), Miller et al.
patent: 6182183 (2001-01-01), Wingard et al.
patent: 6230307 (2001-05-01), Davis et al.
patent: 6324629 (2001-11-01), Kulkarni et al.
patent: 6405160 (2002-06-01), Djaja et al.
patent: 6408163 (2002-06-01), Fik
patent: 6581187 (2003-06-01), Gupta et al.
patent: 6647431 (2003-11-01), Utas
patent: 6671869 (2003-12-01), Davidson et al.
patent: 6735770 (2004-05-01), Yeager et al.
patent: 6794896 (2004-09-01), Brebner
patent: 6891397 (2005-05-01), Brebner
patent: 6904431 (2005-06-01), Holmgren
patent: 6918103 (2005-07-01), Brawn et al.
patent: 7107267 (2006-09-01), Taylor
patent: 7219314 (2007-05-01), Trimberger et al.
patent: 2002/0067717 (2002-06-01), Raschke et al.
patent: 2002/0170038 (2002-11-01), Yeh et al.
patent: 2003/0033374 (2003-02-01), Horn et al.
patent: 2003/0126195 (2003-07-01), Reynolds et al.
patent: 2003/0182083 (2003-09-01), Schwenke et al.
patent: 2004/0006584 (2004-01-01), Vandeweerd
patent: 2004/0071152 (2004-04-01), Wolrich et al.
patent: 2004/0078448 (2004-04-01), Malik et al.
patent: 2004/0083269 (2004-04-01), Cummins
patent: 2004/0128120 (2004-07-01), Coburn et al.
patent: 2004/0187112 (2004-09-01), Potter
patent: 2004/0225965 (2004-11-01), Garside et al.
patent: 2005/0034090 (2005-02-01), Sato et al.
patent: 2005/0114593 (2005-05-01), Cassell et al.
patent: 2005/0172085 (2005-08-01), Klingman
patent: 2005/0172087 (2005-08-01), Klingman
patent: 2005/0172088 (2005-08-01), Klingman
patent: 2005/0172089 (2005-08-01), Klingman
patent: 2005/0172090 (2005-08-01), Klingman
patent: 2005/0172289 (2005-08-01), Klingman
patent: 2005/0172290 (2005-08-01), Klingman
patent: 2005/0177671 (2005-08-01), Klingman
patent: 2005/0210178 (2005-09-01), Klingman
patent: 2005/0223384 (2005-10-01), Klingman
patent: 2005/0262286 (2005-11-01), Klingman
patent: 2006/0041684 (2006-02-01), Daniell et al.
Gordon Brebner; “Multithreading for Logic-Centric Systems”; 12th International Conference on Field Programmable Logic and Applications; Montepellier, France; Sep. 2-4, 2002; Springer LNCS 2438; pp. 5-14.
Gordon Brebner; “Single-chip Gigabit Mixed-version IP Router on Virtex-II Pro”; Proceedings of 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'02); Apr. 2002; IEEE Computer Science Press; pp. 35-44.
Xilinx, Inc.; U.S. Appl. No. 10/402,659, filed Mar. 28, 2003 by James-Roxby.
Xilinx, Inc.; U.S. Appl. No. 10/420,652, filed Apr. 21, 2003 by Brebner.
Xilinx, Inc.; U.S. Appl. No. 10/421,013, filed Apr. 21, 2003 by Brebner.
Xilinx, Inc.; U.S. Appl. No. 10,769,330, filed Jan. 30, 2004 3 by James-Roxby et al.
Xilinx, Inc.; U.S. Appl. No. 10/769,331, filed Jan. 30, 2004 3 by Keller et al.
Xilinx, Inc.; U.S. Appl. No. 10/769,592, filed Jan. 30, 2004 3 by Brebner et al.
U.S. Appl. No. 11/067,431, filed Feb. 25, 2005, Keller et al.
Keller, Eric et al.; “Programming a Hyper-Programmable Architecture for Networked Systems”; published in Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology; Dec. 6-8, 2004; pp. 1-8.
U.S. Appl. No. 12/465,247, filed May 13, 2009, Gordon J. Brebner et al.
Brebner Gordon J.
James-Roxby Philip B.
Keller Eric R.
Kulkarni Chidamber R.
Brush Robert M.
Chiang Jack
Hardaway Michael R.
Tat Binh C
Xilinx , Inc.
LandOfFree
Method and apparatus for application-specific programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for application-specific programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for application-specific programmable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4085659