Method and apparatus for appending buffer areas to requested...

Details Method and apparatus for appending buffer areas to requested... Method and apparatus for appending buffer areas to requested...

2005-01-28

2008-09-23

Elmore, Stephen C. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S135000, C711S154000, C711S170000

Reexamination Certificate

active

07428616

ABSTRACT:
An information processing apparatus has a CPU, a memory, a cache memory and a cache controller. When an acquisition of an area of a prescribed size is requested in the memory, a size equivalent to at least two lines serving as a cache unit is added to the prescribed size requested and this area is reserved in the memory. The area reserved is allocated to an uncacheable memory area of this memory.

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patent: 2005/0091459 (2005-04-01), Quach et al.
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