Method and apparatus for anticipatory power management for low p

Details Method and apparatus for anticipatory power management for low p Method and apparatus for anticipatory power management for low p

1996-04-18

1997-02-04

Harvey, Jack B.

39518212, 39518312, G06F 130

Patent

active

056008414

ABSTRACT:
A method, system, and apparatus for controlling the supply of power to an I/O device attached to a General Purpose Input/Output (GPIO) circuit in a personal digital assistant (PDA) is described. The GPIO circuit, which is responsible for supplying power to the attached I/O device, includes a pin enable circuit coupled to the power pin of the I/O device, where the pin enable circuit includes a contingency register holding a contingency bit and a power register which controls the power supply to the I/O device power pin. The contingency bit is reflective of a power supply priority of the I/O device, where the priority is determined by the type of the I/O device and whether or not the I/O device is recognized. In the event of an unanticipated system powerdown or a power failure, the contents of the power register are replaced with the contingency bit to control the power supply to the I/O device according to the power supply priority specified by the contingency bit, so that unrecognized devices do not receive power during and after the power failure. This is done since unrecognized devices are likely the cause of power failures by demanding more current than the system can provide.

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IBM Technical Disclosure Bulletin, May 1985, vol. 27, pp. 6862-6863.

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