Method and apparatus for analyzing post-layout timing...

Details Method and apparatus for analyzing post-layout timing... Method and apparatus for analyzing post-layout timing...

2005-08-30

2005-08-30

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06938229

ABSTRACT:
A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing violations and presents the foregoing in a report of consolidated timing violations. The report of consolidated timing violations can then be analyzed by a verification engineer.

REFERENCES:
patent: 5095454 (1992-03-01), Huang
patent: 5355321 (1994-10-01), Grodstein et al.
patent: 5371851 (1994-12-01), Pieper et al.
patent: 6141284 (2000-10-01), Weinfurtner
patent: 6427226 (2002-07-01), Mallick et al.
patent: 2003/0046280 (2003-03-01), Rotter et al.

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