Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-04-09
2001-04-24
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06223326
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to analysis of performance and density of logic design modules for integrated circuits, and more particularly to analysis of performance and density of logic designs for programmable gate arrays.
BACKGROUND OF THE INVENTION
Convincing designers to change from a known technology in which they have developed a repertoire of skills to a new technology where the designers' skill-sets are not developed can be challenging. This is the nature of the problem faced by vendors of programmable gate arrays when attempting to convince a buyer that a programmable gate array will meet the buyer's requirements.
Many target customers for programmable gate arrays are designers who presently have ASIC design modules suitable for their applications. The ASIC design modules were likely developed using methodologies and design tools suitable for ASICs. Problems arise in convincing the designers that programmable gate arrays are suitable alternatives to ASICs because an ASIC design module, while perhaps optimally designed for the selected ASIC technology using ASIC design methodologies, may not translate to a programmable gate array design module that satisfies a designer's requirements. Quite often, the reason that an ASIC design module cannot be quickly translated to a design for a programmable gate array that performs acceptably is that the ASIC design module includes ASIC coding and design styles that are not compatible with FPGA design practices. The ASIC design module may also include design elements, for example, adders and multipliers, that are specifically tailored for the ASIC. Oftentimes, in order to convince a designer that a programmable gate array is suitable, field engineers are required to assist in analyzing, redesigning, and determining the performance and gate density of the programmable gate array for a given design. This process may take days or weeks. The outcome of the process may also be dependent on the particular expertise of the field engineer.
Therefore, a method and apparatus that addresses the aforementioned problems is therefore desirable.
SUMMARY OF THE INVENTION
A method and apparatus for analyzing performance and density of a source design module for a target programmable gate array are provided in various embodiments of the invention. The source design module is converted to logic for a selected target programmable gate array. Performance and density of the converted logic are then estimated. If the estimated performance level does not achieve a target performance level, then problematic design elements are automatically converted to approximate functionally equivalent programmable gate array design elements. The performance and density of the target programmable gate array is again estimated using the new design elements. In another mode of operation, design guidance is provided in converting the problematic design elements.
In a first embodiment, a method is provided for analyzing performance of a source design module for a target programmable gate array. The method comprises the steps of: converting the source design module to an approximate functional equivalent programmable gate array design; estimating a first performance level of the programmable gate array using the programmable gate array design; if the first performance level does not achieve a target performance level, performing steps (a)-(c): (a) automatically converting problematic design elements to approximate functionally equivalent programmable gate array design elements; (b) estimating a second performance level of the programmable gate array using the programmable gate array design and converted ones of the design elements; and (c) reporting the second performance level.
In another embodiment, the invention is an apparatus for analyzing performance of a source design module for a target programmable gate array. The apparatus comprises: means for converting the source design module to an approximate functional equivalent programmable gate array design; means for estimating a first performance level of the programmable gate array using the programmable gate array design; means for automatically converting problematic design elements to approximate functionally equivalent programmable gate array design elements if the first performance level does not achieve a target performance level; means for estimating a second performance level of the programmable gate array using the programmable gate array design and converted ones of the design elements if the first performance level does not achieve a target performance level; and means for reporting the second performance level if the first performance level does not achieve a target performance level.
Another method for analyzing performance of a source design module for a target programmable gate array is provided in another embodiment. The method comprises the steps of: converting the source design module to an approximate functional equivalent programmable gate array design; estimating a first performance level of the programmable gate array using the programmable gate array design; comparing the first performance level of the programmable gate array to a target performance level; reporting a conversion success if the first performance level achieves the target performance level; if the first performance level does not achieve the target performance level, performing steps (a)-(e): (a) searching for problematic design elements in the source design module, the problematic design elements indicative of logic portions for which redesign is expected to result in a corresponding improvement in performance of the programmable gate array; (b) reporting the problematic design elements found in the source design module; (c) automatically converting selected ones of the problematic design elements to approximate functional equivalent programmable gate array design elements; (d) estimating a second performance level of the programmable gate array using the programmable gate array design and converted ones of the selected design elements; and (e) reporting the second performance level.
A system for analyzing performance of a source design module for a target programmable gate array is yet another embodiment of the invention. The system comprises: a synthesizer configured and arranged to convert the input source design module to an approximate functional equivalent programmable gate array design; a performance analyzer coupled to the synthesizer and configured and arranged to estimate performance of the programmable gate array design; a design analyzer configured and arranged to identify problematic design elements in the source design module; and a replacement generator coupled to the design analyzer and to the synthesizer and configured and arranged to automatically replace problematic design elements with approximate functionally equivalent programmable gate array design elements.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
REFERENCES:
patent: 6002861 (1999-12-01), Butts et al.
“Synopsys (XSI)—Synthesis and Simulation Design Guide”, 1997, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Fields Carol A.
Tripp Timothy A.
Do Thuan
Maunu LeRoy J.
Smith Matthew
Xilinx , Inc.
Young Edel M.
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