Optics: measuring and testing – Inspection of flaws or impurities – Surface condition
Reexamination Certificate
2002-02-20
2004-02-24
Rosenberger, Richard A. (Department: 2877)
Optics: measuring and testing
Inspection of flaws or impurities
Surface condition
C356S237500
Reexamination Certificate
active
06697153
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for detecting reduced line width(s) over a field/active transition region.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual semiconductor wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using a semiconductor manufacturing tool called an exposure tool or a stepper. Typically, an etch process is then performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as line structures (e.g., polysilicon lines), each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. The manufacturing tools communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1
illustrates a typical semiconductor wafer
105
. The semiconductor wafer
105
typically includes a plurality of individual semiconductor die arranged in a grid
150
. Photolithography steps are typically performed by a stepper on approximately one to four die locations at a time, depending on the specific photomask employed. Photolithography steps are generally performed to form patterned layers of photoresist above one or more process layers that are to be patterned. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features, such as a polysilicon line, or opening-type features, that are to be replicated in an underlying process layer.
Turning now to
FIG. 2A
, a diagram depicting a top view of a portion of a semiconductor wafer comprising a plurality of line structures
155
, is illustrated. In one embodiment, the line structures
155
are formed across a field region
120
and an active region
130
.
FIG. 2B
illustrates a side view diagram of a line structure
155
formed across a field region
120
and an active region
130
. In one embodiment, the field region
120
and the active region
130
are formed on a surface
160
of a silicon substrate
170
. In one embodiment, the line structures
155
are formed above the field region
120
and the active region
130
. One example of the line structure
155
is a poly-silicon line. In one embodiment, the line structure
155
provides an electrical line connection from a gate of a transistor (not shown) to another portion of the transistor.
The line structures
155
, such as polysilicon lines and the like, can contain various errors. One such line structure error is a line edge error, where an excessive amount of roughness exists on the line edges. Errors on line structures can cause current leakage problems, thereby reducing the efficiency of the operation of transistors formed on the semiconductor wafer
105
. Furthermore, line structure errors can result in excessive variations in the operation speed of circuits formed on the semiconductor wafer
105
, such as transistors.
Errors in the line structures
155
can cause quality degradation of the semiconductor wafer
105
being processed. Tests that are used for detecting errors in the line structures
155
can be inefficient and/or destructive in nature, and can be very. time consuming. Often, the tests that are used to detect errors in the line structures
155
can cause interruptions in the production line during semiconductor manufacturing processes.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for analyzing line structures during semiconductor wafer processing. At least one semiconductor wafer
105
is processed. Metrology data from the processed semiconductor wafer
105
is acquired. Film property data from the semiconductor wafer
105
is acquired. Data from a reference library is accessed; the data comprising optical data relating to a line structure formation on a semiconductor wafer
105
, based upon the film property data. The metrology data is compared to data from the reference library. A line structure fault detection analysis is performed in response to the comparison of the metrology data and the reference library data.
In another aspect of the present invention, a system is provided for analyzing line structures during semiconductor wafer
105
processing. The system of the present invention comprises: a computer system; a manufacturing model coupled with the computer system, the manufacturing model being capable of generating and modifying at least one control input parameter signal; a machine interface coupled with the manufacturing model, the machine interface being capable of receiving process recipes from the manufacturing model; a processing tool capable of processing semiconductor wafers
105
and coupled with the machine interface, the first processing tool being capable of receiving at least one control input parameter signal from the machine interface; a metrology tool coupled with the first processing tool and the second processing tool, the metrology tool being capable of acquiring metrology data; an optical data reference library, the optical data reference library comprising optical data related to a plurality of line structures
155
; and an optical data error analysis unit coupled to the metrology tool and the optical data reference library, the scatterometry data error analysis unit capable of comparing the metrology data to corresponding data in the optical data reference library and calculating at least one of a line-edge error and a line structure in response to the comparison.
REFERENCES:
patent: 6051348 (2000-04-01), Marinaro et al.
patent: 6245584 (2001-06-01), Marinaro et al.
patent: 6429943 (2002-08-01), Opsal et al.
patent: 6433878 (2002-08-01), Niu et al.
patent: 6538731 (2003-03-01), Niu et al.
Stirton James B.
Wright Marilyn I.
Advanced Micro Devices , Inc.
Barth Vincent P.
Rosenberger Richard A.
Williams Morgan & Amerson P.C.
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