Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2003-01-21
2004-06-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C326S087000, C327S112000
Reexamination Certificate
active
06751782
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an I/O driver. In particular, the present invention relates to an apparatus and method for analog compensation of driver output signal slew rate against device impedance variation.
BACKGROUND OF THE INVENTION
High speed I/O (input/output) buffers can improve transmitted and received signal quality through the use of on-chip signal termination. One technique that is often used to provide on-chip signal termination is the formation of an Nwell resistor structure as the die termination. Nwell material is often selected due to its highly resistive structure. In addition to being highly resistive, an Nwell structure is simple to create and consumes a relatively small die area compared to, for example a polyresistor.
Unfortunately, Nwell material and Nwell resistive elements created using such material are prone to wide variations in resistivity. In fact, materials and processing used to create resistive elements using Nwell material are subject to wide variations. Therefore, without some sort of external compensation, the resistance of the termination device can easily vary by 300%. Consequently, because output signals are driven through such on-chip resistive termination, the effect of the resistance variation on an output signal slew rate can be significant. Therefore compensation is required to regulate the output driver slew rate according to the strength of the on-chip termination resistor.
As a result, most sensitive high speed output drivers use external compensation to maintain correct functionality across the wide resistive range of the Nwell on-chip termination resistor. Such conventional techniques often utilize a digital approach, which directs the activation and de-activation of various buffers in order to regulate the output drivers. As such, digital regulation of the output drivers is required in order to compensate for the variations in the on-chip resistive termination. Usually, this is performed using a digital compensation block requiring extra pins at higher manufacturing costs.
Accordingly, compensation circuits, particularly ones which employ a digital approach, have historically been trouble spots, due to their complexity, the need for calibration and their potential to interfere with normal buffer operation. In other words, circuit designers are required to provide some sort of compensation mechanism for interfacing with legacy drivers in order to meet timing specifications. Moreover, such compensation mechanisms are required due to the fact that signals subject to inadequate/excessive on-chip termination will incur signaling integrity problems.
As such, signals driven through excessive on-chip termination will incur substantial delays in completing falling/rising signal transition. As a result, the system will incur timing problems, such as violation of set-up time at signal receivers due to the delay in rising/falling signal transition. Conversely, when the on-chip termination resistance is too small, uncontrolled fast signaling of output signal slew rates will result. As a result, this uncontrolled fast switching creates potential signal integrity problems and signal corruption due to reflection. Moreover, electromagnetic interference is aggravated when uncontrolled fast switching of output signals results. Therefore, there remains a need to overcome one or more of the limitations in the above-described, existing art.
REFERENCES:
patent: 5534791 (1996-07-01), Mattos et al.
patent: 6051995 (2000-04-01), Pollachek
patent: 6154083 (2000-11-01), Gaudet et al.
patent: 6353346 (2002-03-01), Chan
patent: 6396137 (2002-05-01), Klughart
patent: 2002/0188915 (2002-12-01), Hayes
Garcia et al., “Design of a Slew Rate Controlled Output Buffer,” IEEE, 1998, pp. 147-150.
Er Kim Soi
Levin Alex
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Siek Vuthe
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