Method and apparatus for an interleaver

Details Method and apparatus for an interleaver Method and apparatus for an interleaver

2006-05-09

2009-08-18

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

Reexamination Certificate

active

07577881

ABSTRACT:
A modem configured to couple to a communication medium for establishing a communication channel thereon. The modem includes an interleaver component configurable as to interleaver parameters ‘I, D’ corresponding to block length and depth respectively. An interleaver memory buffers the communication channel. An interleaver controller controls writing to and reading from the memory of successive data elements of the communication channel with a quantity ‘I’ pairs of write and read pointers. Each pair or write and read pointers identifies memory locations corresponding with an input and output respectively of an associated one of ‘I’ virtual first-in-first-out (‘v-FIFO’) buffers in the memory. Control of the pointers required to read out the stored data elements in interleaved fashion is limited to shifting all pointers uniformly by one address block in each interleaver block cycle, which simplifies pointer management.

REFERENCES:
patent: 4843607 (1989-06-01), Tong
patent: 2006/0107174 (2006-05-01), Heise

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