Method and apparatus for an in-situ victim cache

Details Method and apparatus for an in-situ victim cache Method and apparatus for an in-situ victim cache

2006-04-11

2006-04-11

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S134000

Reexamination Certificate

active

07028144

ABSTRACT:
A method and apparatus for a microprocessor with a cache that has the advantages given by a victim cache without physically having a victim cache is disclosed. In one embodiment, a victim flag may be associated with each way in a set. At eviction time, the way whose victim flag is true may be evicted. However, the victim flag may be reset to false if a superceding request arrives for the cache line in that way. Another cache line in another way may then have its victim flag made true.

REFERENCES:
patent: 5564035 (1996-10-01), Lai
patent: 6061765 (2000-05-01), Van Doren et al.
patent: 6128702 (2000-10-01), Saulsbury et al.
patent: 6249846 (2001-06-01), Van Doren et al.
patent: 2004/0215890 (2004-10-01), Cargnoni et al.
Barroso, L.A. et al., “Piranha: a scalable architecture based on single-chip multiprocessing”, Proceedings of the 27thAnnual International Symposium on Computer Architecture, Vancouver, BC, Canada, pp. 282-293 (Jun. 10-14, 2000).

Affiliated with

Also associated with

Rating

Method and apparatus for an in-situ victim cache does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for an in-situ victim cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for an in-situ victim cache will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3617360