Method and apparatus for an in-situ victim cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S134000

Reexamination Certificate

active

07028144

ABSTRACT:
A method and apparatus for a microprocessor with a cache that has the advantages given by a victim cache without physically having a victim cache is disclosed. In one embodiment, a victim flag may be associated with each way in a set. At eviction time, the way whose victim flag is true may be evicted. However, the victim flag may be reset to false if a superceding request arrives for the cache line in that way. Another cache line in another way may then have its victim flag made true.

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Barroso, L.A. et al., “Piranha: a scalable architecture based on single-chip multiprocessing”, Proceedings of the 27thAnnual International Symposium on Computer Architecture, Vancouver, BC, Canada, pp. 282-293 (Jun. 10-14, 2000).

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