Method and apparatus for an asynchronous pulse logic circuit

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

Reexamination Certificate

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C326S026000, C326S027000, C326S083000

Reexamination Certificate

active

06949954

ABSTRACT:
The present invention is a class of circuits named asynchronous pulse logic (APL) circuit and designing methods for such circuits. APL replaces two of the four-phase handshakes in QDI circuits with pulses, thus breaking the timing dependencies that cause performance problems in QDI circuits. Since the pulse length in APL varies so little, it can be assumed constant. This assumption frees designers from needing to consider the effects of the inputs and outputs on the pulse length, which means timing properties can be verified locally. One embodiment of the present invention is a class of circuit design called the single-track-handshake-asynchronous-pulse-logic (STAPL), which serves as a new target for the compilation of CHP (Communication Hardware Process) programs. In one embodiment, a five-stage pulse generator is used to create a 10 transition count cycle circuit. Advantages of STAPL include a simplified solution to the charge-sharing problem and less loading from p-transistors.

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patent: 6433601 (2002-08-01), Ganesan

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