Method and apparatus for amplifying a signal to produce a latche

Details Method and apparatus for amplifying a signal to produce a latche Method and apparatus for amplifying a signal to produce a latche

1998-02-02

1999-08-24

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365148, 36518905, 365194, 365208, G11C 1300

Patent

active

059432748

ABSTRACT:
Method and apparatus for amplifying a signal (50) to produce a latched digital signal (46). In one embodiment, an output stage circuit (24) of memory (10) includes a differential amplifier circuit (100), a level converter (102), a timing circuit (104), a clock-free latch (106), a high impedance control circuit (108), a high impedance control circuit (110), and an output driver (112). Output stage (24) requires one clock signal to function. Alternate embodiments may skew the disabling edge of the clock to improve the speed characteristics of output stage (24). In one embodiment, signal (50) is a differential pair of signals provided from a memory bit cell array (12).

REFERENCES:
patent: 5515334 (1996-05-01), Kotani et al.
patent: 5680066 (1997-10-01), Akioka et al.
patent: 5703827 (1997-12-01), Leung et al.
patent: 5781480 (1998-07-01), Nogle et al.
patent: 5798972 (1998-08-01), Lao et al.

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