Method and apparatus for aligning the phases of digital...

Details Method and apparatus for aligning the phases of digital... Method and apparatus for aligning the phases of digital...

2011-05-24

2011-05-24

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Reliability

C326S010000, C326S015000, C326S093000

Reexamination Certificate

active

07948260

ABSTRACT:
A method and apparatus for aligning the phases of digital clock signals are disclosed. For example, a phase alignment circuit according to one embodiment includes a frequency adjuster comprising a first plurality of inputs, where at least some of the first plurality of inputs are coupled to an output of a digital clock of an integrated circuit, a phase adjuster comprising a second plurality of inputs, where at least some of the second plurality of inputs are coupled to a plurality of outputs of the frequency adjuster, and an XOR gate comprising a third plurality of inputs, each of the third plurality of inputs being coupled to one of the plurality of outputs of the frequency adjuster.

REFERENCES:
patent: 2007/0090887 (2007-04-01), Seefeldt et al.
patent: 2010/0271090 (2010-10-01), Rasmussen

Affiliated with

Also associated with

Rating

Method and apparatus for aligning the phases of digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for aligning the phases of digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for aligning the phases of digital... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2663974