Method and apparatus for aligning multiple outputs of an FPGA

Details Method and apparatus for aligning multiple outputs of an FPGA Method and apparatus for aligning multiple outputs of an FPGA

2007-03-09

2008-12-16

Feliciano, Eliseo Ramos (Department: 2857)

Data processing: measuring, calibrating, or testing

Calibration or correction system

Circuit tuning

C375S219000, C375S354000, C713S401000

Reexamination Certificate

active

07467056

ABSTRACT:
Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.

REFERENCES:
patent: 6167077 (2000-12-01), Ducaroir et al.
patent: 6999891 (2006-02-01), Pepper
patent: 7036037 (2006-04-01), Paul et al.
patent: 7170907 (2007-01-01), Reches
patent: 2004/0252684 (2004-12-01), Evans et al.
patent: 2004/0264613 (2004-12-01), Buchmann et al.
Serdes Framer Interface Level 5 (SFI-5) Implementation Agreement for 40GB/s Interface for Physical Layer Devices (IOF-SFI5-01.02), Jan. 29, 2002.
IA Title: Serdes Framer Interface Level 5 Phase 2 (SFI-5.2): Implementation Agreement for 40GB/s Interface for Physical Layer Devices (IOF-SFI5-02), Oct. 2, 2006.

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