Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-07-19
2005-07-19
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C375S373000, C375S376000
Reexamination Certificate
active
06920622
ABSTRACT:
An integrated circuit receives a request to adjust the phase of an output clock being generated by a phase-locked loop based on an input reference clock. A digital or analog offset value is injected into the phase-locked loop based on a phase adjustment amount contained in the phase adjustment request. Alternatively, a programmable delay is implemented in the PLL feedback path or the reference clock path. The delay is based on the phase adjustment request.
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Garlepp Bruno
Huang Yunteng
Rossoshek Helen
Siek Vuthe
Silicon Laboratories Inc.
Zagorin O'Brien Graham LLP
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