Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-12-12
2006-12-12
Eillis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
Reexamination Certificate
active
07149856
ABSTRACT:
A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.
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Barth Richard M.
Chau Pak Shing
Davis Paul G.
Donnelly Kevin S.
Garlepp Bruno Werner
Eillis Kevin L.
Magen Vierra
Marcus & DeNiro LLP
Rambus Inc.
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